Patents by Inventor Andy Chuang

Andy Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010045668
    Abstract: A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.
    Type: Application
    Filed: April 8, 1999
    Publication date: November 29, 2001
    Inventors: FU-TAI LIOU, ANDY CHUANG
  • Patent number: 6320254
    Abstract: A plug structure capable of directly coupling to a packageless bonding pad without having to go through a third conductive medium. The plug structure includes several plugs on a base substrate, such as a printed circuit board or a carrier. A solder is disposed on the plug surface in which the plug can be a cylinder or mushroom-like shape and the solder can be a film or a ball.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: November 20, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Fu-Tai Liou, Andy Chuang
  • Patent number: 6180515
    Abstract: A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: January 30, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Andy Chuang
  • Patent number: 6153479
    Abstract: A method of fabricating shallow trench isolation structures. A substrate is provided and a masking layer and an oxide layer are formed respectively on the substrate. The masking layer, the oxide layer and the substrate are defined and an opening is formed within the substrate. A portion of masking layer and the oxide layer are removed and an insulating material is later formed to fill with the opening. The masking layer is removed and the shallow trench isolation structure of this invention is therefore achieved.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: November 28, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Wu Liao, Andy Chuang, Chien-Li Kuo
  • Patent number: 6093609
    Abstract: A method has a feature that one side of the spacers surrounding a gate of a MOS transistor is removed and another side of the spacers is exposed. By the method of this invention, the gate, the source and the pick-up region of a well are electrically connected by a plug through a silicide layer covering them. Furthermore, the pick-up region is adjacent to the source such that the effective surface area can be reduced and the process has a higher error tolerance.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: July 25, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Andy Chuang
  • Patent number: 6054362
    Abstract: A method of patterning a dummy layer is provided using the dark/clear ratio. First, the area of devices and the area of relevant devices are defined. The relevant devices are usually positioned around the devices. The devices, the relevant devices, and other regions are united according to the design rules to form a non-dummy pattern region. Then a dummy pattern region is defined. There are many dummy bulks in the dummy pattern region. Next, a known dark/clear ratio of the non-dummy pattern region is provided. A density of the dummy patterns is obtained from the known dark/clear ratio, the length of the dummy bulk, the width of the dummy bulk and a equation. The equation is as follows: the known dark/clear ratio=(the length-the parameter)(the width-the parameter)/[the length.times.the width-(the length-the parameter)(the width-the parameter)]. After obtaining the parameter, each dummy bulk is divided into two regions including a clear region and a dark region.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: April 25, 2000
    Assignee: United Microelectronics Corp.
    Inventor: Andy Chuang
  • Patent number: 6008080
    Abstract: An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: December 28, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Andy Chuang, Tzong-Shien Wu, Sun-Chieh Chien
  • Patent number: 5962342
    Abstract: An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: October 5, 1999
    Assignee: United Microelectronics Corporation
    Inventors: Andy Chuang, Tzung-Han Lee
  • Patent number: 5936279
    Abstract: A gate oxide layer, a polysilicon layer are patterned on a substrate. Then, a thermal oxidation is carried out to form the first silicon dioxide layer on the surface of the polysilicon layer. Then, a first silicon nitride layer is patterned on the first silicon dioxide layer, over the top of the polysilicon layer. Then, a second silicon nitride layer is formed on the first silicon dioxide layer and the first silicon nitride layer. Next, a second silicon dioxide layer is formed on the second silicon nitride layer. Then, an etching technique is used to form the side-wall spacers. The side-wall spacers composed of silicon nitride layer and silicon dioxide layer. A dielectric layer is formed on the cap layer, side-wall spacers and silicon dioxide layer. An etch with high selectivity is used to etch the dielectric layer to create a contact hole.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: August 10, 1999
    Assignee: United microelectronics Corp.
    Inventor: Andy Chuang
  • Patent number: 5814553
    Abstract: The process of the present invention has numerous advantages over the prior art. The silicon nitride side-wall spacers permit a small contact hole thus miniaturizing the cell beyond lithographic limits. The side-wall spacers composed of silicon nitride and silicon dioxide avoid to expose the polysilicon when the contact window is formed by etching step. Moreover, the highly selective etching process improve the accuracy of the contact window.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: September 29, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Andy Chuang, Tzong-Shien Wu