Patents by Inventor Andy Cowley
Andy Cowley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7786007Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: GrantFiled: April 7, 2008Date of Patent: August 31, 2010Assignee: Infineon Technologies AGInventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Publication number: 20080213993Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: ApplicationFiled: April 7, 2008Publication date: September 4, 2008Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Patent number: 7368804Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: GrantFiled: May 16, 2003Date of Patent: May 6, 2008Assignee: Infineon Technologies AGInventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
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Patent number: 7241681Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: January 12, 2006Date of Patent: July 10, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Patent number: 7125792Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: October 24, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Douglas C. La Tulipe, Timothy Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht
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Patent number: 7091612Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: GrantFiled: October 14, 2003Date of Patent: August 15, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Patent number: 7060619Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.Type: GrantFiled: March 4, 2003Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Andy Cowley, Erdem Kaltalioglu, Mark Hoinkis, Michael Stetter
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Publication number: 20060113278Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: ApplicationFiled: January 12, 2006Publication date: June 1, 2006Inventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew Simon, Mark Hoinkis, Steffen Kaldor, Chih-Chao Yang
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Patent number: 7052621Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: GrantFiled: June 13, 2003Date of Patent: May 30, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Patent number: 7041574Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.Type: GrantFiled: July 19, 2004Date of Patent: May 9, 2006Assignee: Infineon Technologies AGInventors: Sun-Oo Kim, Markus Naujok, Andy Cowley
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Publication number: 20050221610Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: ApplicationFiled: June 3, 2005Publication date: October 6, 2005Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis Warner, Erdem Kaltalioglu
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Publication number: 20050208742Abstract: A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William America, Larry Clevenger, Andy Cowley, Timothy Dalton, Mark Hoinkis, Kaushik Kumar, Douglas La Tulipe
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Publication number: 20050077628Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Inventors: Kaushik Kumar, Timothy Dalton, Larry Clevenger, Andy Cowley, Douglas La Tulipe, Mark Hoinkis, Chih-Chao Yang, Yi-Hsiung Lin, Erdem Kaltalioglu, Markus Naujok, Jochen Schacht
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Publication number: 20050079706Abstract: A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.Type: ApplicationFiled: October 14, 2003Publication date: April 14, 2005Inventors: Kaushik Kumar, Douglas La Tulipe, Timothy Dalton, Larry Clevenger, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht
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Patent number: 6872648Abstract: The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.Type: GrantFiled: September 19, 2002Date of Patent: March 29, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Gerald R. Friese, Andy Cowley, Mohammed Fazil Fayaz, William T. Motsiff
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Patent number: 6864171Abstract: Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.Type: GrantFiled: October 9, 2003Date of Patent: March 8, 2005Assignee: Infineon Technologies AGInventors: Mark D. Hoinkis, Matthias P. Hierlemann, Mohammed Fazil Fayaz, Andy Cowley, Erdum Kaltalioglu
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Publication number: 20040259273Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.Type: ApplicationFiled: July 19, 2004Publication date: December 23, 2004Inventors: Sun-Oo Kim, Markus Naujok, Andy Cowley
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Publication number: 20040251234Abstract: A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).Type: ApplicationFiled: June 13, 2003Publication date: December 16, 2004Inventors: Kaushik Kumar, Lawrence Clevenger, Timothy Dalton, Douglas C. La Tulipe, Andy Cowley, Erdem Kaltalioglu, Jochen Schacht, Andrew H. Simon, Mark Hoinkis, Steffen K. Kaldor, Chih-Chao Yang
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Publication number: 20040248400Abstract: A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.Type: ApplicationFiled: June 9, 2003Publication date: December 9, 2004Inventors: Sun-Oo Kim, Markus Naujok, Andy Cowley
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Publication number: 20040227214Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.Type: ApplicationFiled: May 16, 2003Publication date: November 18, 2004Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu