Abstract: The invention provides a low power consumption cache memory structure. In the present invention, the tag memory is accessed first and then the comparison is made. If there is a hit, only the correct bank of the array will be accessed, instead of all of the banks, thereby saving power. For example, if the array has four banks, then only one of the four banks will be read, saving the power required to read the other three banks. In addition, each array bank is divided into sub-banks called vertical banks. Each array bank is composed of cache lines, where each line stores several data words. Instead of powering up all of the lines in one array bank to read the desired data, only a subset of lines will be powered up, and each subset is a vertical bank. The vertical bank selection is made by decoding certain bits of the input address.