Patents by Inventor ANDY GLAISTER
ANDY GLAISTER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9529575Abstract: Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct). Moreover, the transformed shader program is amenable to optimization via existing compiler technology, and can be executed efficiently by CPU thread(s). A Dispatch call can be load-balanced on a CPU by assigning single or multiple CPU threads to execute thread blocks. In addition, the number of concurrently executing thread blocks do not overload the CPU.Type: GrantFiled: February 16, 2012Date of Patent: December 27, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Patent number: 9430199Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.Type: GrantFiled: February 16, 2012Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Patent number: 8806458Abstract: Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.Type: GrantFiled: February 16, 2012Date of Patent: August 12, 2014Assignee: Microsoft CorporationInventors: Andy Glaister, Blaise Pascal Tine, Blake Pelton, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Patent number: 8698818Abstract: Systems, methods, and computer-readable media for optimizing emulated fixed-function and programmable graphics operations are provided. Data comprising fixed function and programmable states for an image or scenario to be rendered is received. The data for the image is translated into operations. One or more optimizations are applied to the operations. The optimized operations are implemented to render the scenario.Type: GrantFiled: May 15, 2008Date of Patent: April 15, 2014Assignee: Microsoft CorporationInventors: Blake Pelton, Andy Glaister, Mikhail Lyapunov, Steve Kihslinger, David Tuft
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Publication number: 20130215117Abstract: Described are compiler algorithms that partition a compute shader program into maximal-size regions, called thread-loops. The algorithms may remove original barrier-based synchronization yet the thus-transformed shader program remains semantically equivalent to the original shader program (i.e., the transformed shader program is correct). Moreover, the transformed shader program is amenable to optimization via existing compiler technology, and can be executed efficiently by CPU thread(s). A Dispatch call can be load-balanced on a CPU by assigning single or multiple CPU threads to execute thread blocks. In addition, the number of concurrently executing thread blocks do not overload the CPU.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: Microsoft CorporationInventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Publication number: 20130219378Abstract: Intermediate representation (IR) code is received as compiled from a shader in the form of shader language source code. The input IR code is first analyzed during an analysis pass, during which operations, scopes, parts of scopes, and if-statement scopes are annotated for predication, mask usage, and branch protection and predication. This analysis outputs vectorization information that is then used by various sets of vectorization transformation rules to vectorize the input IR code, thus producing vectorized output IR code.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: Microsoft CorporationInventors: Andy Glaister, Blaise Pascal Tine, Blake Pelton, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Publication number: 20130219377Abstract: Described herein are optimizations of thread loop intermediate representation (IR) code. One embodiment involves an algorithm that, based on data-flow analysis, computes sets of temporary variables that are loaded at the beginning of a thread loop and stored upon exit from a thread loop. Another embodiment involves reducing the size of a thread loop trip for a commonly-found case where a piece of compute shader is executed by a single thread (or a compiler-analyzable range of threads). In yet another embodiment, compute shader thread indices are cached to avoid excessive divisions, further improving execution speed.Type: ApplicationFiled: February 16, 2012Publication date: August 22, 2013Applicant: MICROSOFT CORPORATIONInventors: Andy Glaister, Blaise Pascal Tine, Derek Sessions, Mikhail Lyapunov, Yuri Dotsenko
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Publication number: 20090284535Abstract: Systems, methods, and computer-readable media for optimizing emulated fixed-function and programmable graphics operations are provided. Data comprising fixed function and programmable states for an image or scenario to be rendered is received. The data for the image is translated into operations. One or more optimizations are applied to the operations. The optimized operations are implemented to render the scenario.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: MICROSOFT CORPORATIONInventors: BLAKE PELTON, ANDY GLAISTER, MIKHAIL LYAPUNOV, STEVE KIHSLINGER, DAVID TUFT