Patents by Inventor ANDY HSIEH

ANDY HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11553710
    Abstract: An antibacterial and deodorizing leather includes a leather body and an antibacterial and deodorizing layer. The antibacterial and deodorizing layer includes a water-based foaming material and an antibacterial deodorant. The water-based foaming material and the antibacterial deodorant are mixed and arranged on the leather body and then bonded with the leather body by hot pressing. By uniformly mixing the antibacterial deodorant and a bactericide through the water-based foaming material to become gelatinous, the antibacterial and deodorizing layer is arranged on the leather body according to the size of the leather body. Then, the antibacterial and deodorizing layer is tightly bonded with the leather body by hot pressing, achieving the effects of saving costs, simplifying the manufacturing process, and environmental protection.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 17, 2023
    Assignee: Fu Hsing Leather Co., Ltd.
    Inventors: Andy Hsieh, Jason Hsieh
  • Publication number: 20210386058
    Abstract: An antibacterial and deodorizing leather includes a leather body and an antibacterial and deodorizing layer. The antibacterial and deodorizing layer includes a water-based foaming material and an antibacterial deodorant. The water-based foaming material and the antibacterial deodorant are mixed and arranged on the leather body and then bonded with the leather body by hot pressing. By uniformly mixing the antibacterial deodorant and a bactericide through the water-based foaming material to become gelatinous, the antibacterial and deodorizing layer is arranged on the leather body according to the size of the leather body. Then, the antibacterial and deodorizing layer is tightly bonded with the leather body by hot pressing, achieving the effects of saving costs, simplifying the manufacturing process, and environmental protection.
    Type: Application
    Filed: August 6, 2020
    Publication date: December 16, 2021
    Inventors: ANDY HSIEH, JASON HSIEH
  • Patent number: 9658396
    Abstract: Described herein are an apparatus, system, and method for providing a vertical optical coupler (VOC) for planar photonics circuits such as photonics circuits fabricated on silicon-on-insulator (SOI) wafers. In one embodiment, the VOC comprises a waveguide made from a material having refractive index in a range of 1.45 to 3.45, the waveguide comprising: a first end configured to reflect light nearly vertical by total internal reflection between the waveguide and another medium, a second end to receive the light for reflection, and a third end to output the reflected light. The VOC couples with a Si waveguide having a first region including: a first end to receive light; and an inverted tapered end in the direction of light propagation to output the received light, wherein the inverted tapered end of the Si waveguide is positioned inside the waveguide.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Haisheng Rong, Ofir Gan, Pradeep Srinivasan, Assia Barkai, I-Wei Andy Hsieh, Mahesh Krishnamurthi, Yun-Chung Neil Na
  • Publication number: 20140205234
    Abstract: Described herein are an apparatus, system, and method for providing a vertical optical coupler (VOC) for planar photonics circuits such as photonics circuits fabricated on silicon-on-insulator (SOI) wafers. In one embodiment, the VOC comprises a waveguide made from a material having refractive index in a range of 1.45 to 3.45, the waveguide comprising: a first end configured to reflect light nearly vertical by total internal reflection between the waveguide and another medium, a second end to receive the light for reflection, and a third end to output the reflected light. The VOC couples with a Si waveguide having a first region including: a first end to receive light; and an inverted tapered end in the direction of light propagation to output the received light, wherein the inverted tapered end of the Si waveguide is positioned inside the waveguide.
    Type: Application
    Filed: September 29, 2011
    Publication date: July 24, 2014
    Inventors: Haisheng Rong, Ofir Gan, Pradeep Sirnivasan, Assia Barkal, I-Wel Andy Hsieh, Mahesh Kirshamurthi, Yun-Chung Neil Na
  • Patent number: 8588570
    Abstract: Instead of monitoring the optical power coming out of a waveguide, a direct method of monitoring the optical power inside the waveguide without affecting device or system performance is provided. A waveguide comprises a p-i-n structure which induces a TPA-generated current and may be enhanced with reverse biasing the diode. The TPA current may be measured directly by probing metal contacts provided on the top surface of the waveguide, and may enable wafer-level testing. The p-i-n structures may be implemented at desired points throughout an integrated network, and thus allows probing of different devices for in-situ power monitor and failure analysis.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 19, 2013
    Assignee: Intel Corporation
    Inventors: Haisheng Rong, I-Wei Andy Hsieh, Mario J. Paniccia
  • Publication number: 20120080672
    Abstract: Instead of monitoring the optical power coming out of a waveguide, a direct method of monitoring the optical power inside the waveguide without affecting device or system performance is provided. A waveguide comprises a p-i-n structure which induces a TPA-generated current and may be enhanced with reverse biasing the diode. The TPA current may be measured directly by probing metal contacts provided on the top surface of the waveguide, and may enable wafer-level testing. The p-i-n structures may be implemented at desired points throughout an integrated network, and thus allows probing of different devices for in-situ power monitor and failure analysis.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: HAISHENG RONG, I-WEI ANDY HSIEH, MARIO J. PANICCIA