Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Abstract: Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Abstract: Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

Abstract: In one embodiment, an integrated circuit includes a pass gate circuit and a memory element circuit. The pass gate circuit receives a user signal that toggles between a high voltage level and a low voltage level. The memory element circuit outputs a control signal to control the pass gate circuit. The control signal may be asserted to be greater than the high voltage level when activating the pass gate circuit or the control signal may be deasserted to be less than the low voltage level when deactivating the pass gate circuit. In addition to that, a method on how to operate the pass gate circuit is also provided.

Abstract: Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.

Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract: A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.

Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.