Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: A programmable integrated circuit has multiple power supply voltages. Power supply voltages are distributed using power supply distribution lines. The integrated circuit has programmable power supply voltage selection switches. Each power supply voltage selection switch has its inputs connected to the power supply distribution lines and supplies a selected power supply voltage to a circuit block at its output. Test circuits are provided for testing the power supply voltage selection switches. During testing, the power supply voltage selection switches are adjusted to produce various power supply voltages at their outputs. The test circuit associated with each switch performs voltage comparisons to determine whether the switch is functioning properly. Each test circuit produces a test result based on its voltage comparison. The test results from the test circuits are provided to a scan chain, which unloads the test results from the integrated circuit to a tester for analysis.

Abstract: A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT.

Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

Abstract: The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

Abstract: A memory block of a programmable device uses a double data rate communication scheme to communicate data with logic cells at a rate of two bits per clock cycle per data line. The memory block can be configured to use the double data rate communication scheme or a single data rate communication scheme. The memory block can switch between either communications scheme as needed to communicate with different portions of the programmable device. If a memory block of a programmable device includes two or more data access ports, an embodiment of a programmable device allows each data access port to be configured for single data rate or double data rate communications independently of other data ports. Any arbitrary logic cell of the programmable device can communicate with a memory block using the double data rate communication scheme by configuring additional logic cells to operate as a double data rate interface.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.

Abstract: Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.

Abstract: The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated with a group of read data signals. The soft core logic circuit dynamically determines an appropriate phase-shift value for the read strobe signal and adjusts the phase-shift to accommodate the environmental changes. The soft core logic circuit also introduces into the PLD various intermediate signals from a phase-shift estimator and a programmable phase delay chain.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract: Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

Abstract: Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a sensitivity processor. The error detection circuit detects the presence of errors. The sensitivity processor determines whether a detected error can be ignored, or whether remedial action, such as providing an error flag, reconfiguring the device, or correcting the error, should be commenced. The sensitivity processor may make this determination based on whether the error occurred in a memory cell that configures unused circuitry. The sensitivity processor may make use of an error log to track known errors that may be ignored, so that this determination does not need to be done each time the configuration data is checked.

Abstract: A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.

Abstract: Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.