Abstract: Systems and methods of the present disclosure may provide efficient power consumption for programmable logic devices based on unused portions of programmable logic. A programmable logic device includes a plurality of programmable logic sectors that implement a circuit design, unused portions of the programmable logic device, and interconnection resources. The interconnection resources include a multiplexer that receives a control signal and that generates an output signal based on the control signal and a driver that receives the output signal and that implements a low-power mode to reduce leakage current.

Abstract: Systems and methods of the present disclosure may provide efficient power consumption for programmable logic devices based on unused portions of programmable logic. A programmable logic device includes a plurality of programmable logic sectors that implement a circuit design, unused portions of the programmable logic device, and interconnection resources. The interconnection resources include a multiplexer that receives a control signal and that generates an output signal based on the control signal and a driver that receives the output signal and that implements a low-power mode to reduce leakage current.

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.