Abstract: Among other things, embodiments of the present disclosure improve the functionality of electronic messaging software and systems by allowing senders to transmit messages and content using a messaging system, and recipients to access such messages and content, even if the recipients do not have access to the messaging system.

Abstract: In some aspects, a method of carbonation control can include monitoring, via a first sensor, an environmental condition in a contactor unit, the contactor unit including a plurality of carbonation vessels including carbonation medium, monitoring, via a second sensor, an environmental condition at a location outside of the contactor unit, predicting, based on the measured environmental condition in the contactor unit and the measured environmental condition at the location outside of the contactor unit, a local humidity in a carbonation vessel from the plurality of carbonation vessels, a water content of the carbonation medium in the carbonation vessel from the plurality of carbonation vessels, and a carbonation extent of the carbonation medium in the carbonation vessel from the plurality of carbonation vessels for a carbonation forecasting period, and executing an action on the plurality of carbonation vessels based on the predicted water content and predicted carbonation extent.

Abstract: An information handling system including a processor; a battery; a charger module a voltage regulator module connected between the charger module and the processor, the voltage regulator module configured to receive power from the charger module and provide a regulated voltage to the processor; a OVP module configured to determine that the regulated voltage output from the voltage regulator module is above a first threshold, and in response, provide a first signal to the charger module to indicating that the regulated voltage is above the first threshold; a UVP module configured to determine that the charger voltage output from the charger module is below a second threshold, and in response, provide a second signal to the charger module indicating that the charger voltage is below the second threshold, wherein the charger module, in response to receiving both the first signal and the second signal, changes to an off power state.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for polling a battery management unit (BMU) that is coupled to a battery power source, the polling including identifying parameters associated with the battery power source and are stored by registers; determining that an AC power source is not actively providing power to the IHS; determining that the battery power source does not support dynamic battery power technology (DBPT); determining that the RSoC of the battery power source is greater than a first threshold percentage and less than a second threshold percentage; determining an updated processor peak power (PPP) value based on i) the RSOC, ii) a minimum PPP of the processor at the first threshold percentage, and iii) a maximum PPP of the processor at the second threshold percentage; and updating the registers based on the updated PPP.

Abstract: An information handling system including a processor; a battery; a charger module a voltage regulator module connected between the charger module and the processor, the voltage regulator module configured to receive power from the charger module and provide a regulated voltage to the processor; a OVP module configured to determine that the regulated voltage output from the voltage regulator module is above a first threshold, and in response, provide a first signal to the charger module to indicating that the regulated voltage is above the first threshold; a UVP module configured to determine that the charger voltage output from the charger module is below a second threshold, and in response, provide a second signal to the charger module indicating that the charger voltage is below the second threshold, wherein the charger module, in response to receiving both the first signal and the second signal, changes to an off power state.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for polling a battery management unit (BMU) that is coupled to a battery power source, the polling including identifying parameters associated with the battery power source and are stored by registers; determining that an AC power source is not actively providing power to the IHS; determining that the battery power source does not support dynamic battery power technology (DBPT); determining that the RSoC of the battery power source is greater than a first threshold percentage and less than a second threshold percentage; determining an updated processor peak power (PPP) value based on i) the RSOC, ii) a minimum PPP of the processor at the first threshold percentage, and iii) a maximum PPP of the processor at the second threshold percentage; and updating the registers based on the updated PPP.

Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

Abstract: A computing system is provided that includes a distribution endpoint including one or more processors configured to receive a request from a developer computing device to update a program managed by the distribution endpoint, the program being previously packaged and signed. The one or more processors of the distribution endpoint are further configured to receive a code file including a change to the program, retrieve a package of the program that has not been updated with the change to the program, generate an updated package of the program by adding the code file to the retrieved package of the program such that the updated package of the program logically represents a package of the updated program, and distribute the updated package of the program to an end user computing device.

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.

Abstract: A computing system is provided that includes a distribution endpoint including one or more processors configured to receive a request from a developer computing device to update a program managed by the distribution endpoint, the program being previously packaged and signed. The one or more processors of the distribution endpoint are further configured to receive a code file including a change to the program, retrieve a package of the program that has not been updated with the change to the program, generate an updated package of the program by adding the code file to the retrieved package of the program such that the updated package of the program logically represents a package of the updated program, and distribute the updated package of the program to an end user computing device.