Patents by Inventor Andy Lo
Andy Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923441Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20220399457Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: August 16, 2022Publication date: December 15, 2022Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Patent number: 11450759Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: September 30, 2020Date of Patent: September 20, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Patent number: 11373871Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.Type: GrantFiled: September 20, 2019Date of Patent: June 28, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Benjamin Colombeau, Wolfgang R. Aderhold, Andy Lo, Yi-Chiau Huang
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Publication number: 20220123123Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.Type: ApplicationFiled: October 11, 2021Publication date: April 21, 2022Applicant: Applied Materials, Inc.Inventors: Myungsun Kim, Andy Lo, Eric Davey, Michael Stolfi, Benjamin Colombeau
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Publication number: 20220037529Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.Type: ApplicationFiled: July 28, 2021Publication date: February 3, 2022Applicant: Applied Materials, Inc.Inventors: Myungsun Kim, Michael Stolfi, Benjamin Colombeau, Andy Lo
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Patent number: 11195923Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.Type: GrantFiled: November 8, 2019Date of Patent: December 7, 2021Assignee: Applied Materials, Inc.Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Vidyadhar Mandrekar, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
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Patent number: 11152479Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.Type: GrantFiled: January 27, 2020Date of Patent: October 19, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
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Publication number: 20210104617Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: ApplicationFiled: September 30, 2020Publication date: April 8, 2021Applicant: Applied Materials, Inc.Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Publication number: 20200258997Abstract: The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes forming a source/drain region in a processing system, forming a doped semiconductor layer on the source/drain region in the processing system, forming a metal silicide layer, forming a dielectric material, forming a trench in the dielectric material, and filling the trench with a conductor. The source/drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.Type: ApplicationFiled: January 27, 2020Publication date: August 13, 2020Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
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Publication number: 20200203490Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.Type: ApplicationFiled: November 8, 2019Publication date: June 25, 2020Inventors: Gaurav THAREJA, Xuebin LI, Abhishek DUBE, Yi-Chiau HUANG, Tushar Vidyadhar MANDREKAR, Andy LO, Patricia M. LIU, Sanjay NATARAJAN, Saurabh CHOPRA
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Publication number: 20200161134Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.Type: ApplicationFiled: September 20, 2019Publication date: May 21, 2020Inventors: BENJAMIN COLOMBEAU, WOLFGANG R. ADERHOLD, ANDY LO, YI-CHIAU HUANG
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Patent number: 9419661Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: GrantFiled: October 19, 2015Date of Patent: August 16, 2016Assignee: Maxlinear, IncInventors: Andy Lo, Sugbong Kang
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Publication number: 20160049971Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: ApplicationFiled: October 19, 2015Publication date: February 18, 2016Inventors: Andy Lo, Sugbong Kang
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Patent number: 9166637Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: GrantFiled: July 28, 2014Date of Patent: October 20, 2015Assignee: MAXLINEAR, INC.Inventors: Andy Lo, Sugbong Kang
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Patent number: 9124338Abstract: A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated.Type: GrantFiled: June 3, 2013Date of Patent: September 1, 2015Assignee: MaxLinear, Inc.Inventors: Curtis Ling, Andy Lo, Tete Sedalo
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Publication number: 20150030110Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: ApplicationFiled: July 28, 2014Publication date: January 29, 2015Inventors: Andy Lo, Sugbong Kang
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Patent number: 8792543Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: GrantFiled: July 15, 2013Date of Patent: July 29, 2014Assignee: MaxLinear, Inc.Inventors: Andy Lo, Sugbong Kang
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Publication number: 20140155012Abstract: A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated.Type: ApplicationFiled: June 3, 2013Publication date: June 5, 2014Inventors: Curtis Ling, Andy Lo, Tete Sedalo
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Publication number: 20130301766Abstract: An impulse noise mitigation circuit (INMC) may set a cut-off frequency of each of two high pass filters to bound a frequency bandwidth of a desired signal, wherein a first of the two filters allows frequencies higher than the frequency bandwidth of the desired signal, and a second of the two filters allows frequencies lower than the frequency bandwidth of the desired signal. The INMC may compute and store a mean magnitude separately for a first signal response of the first filter and a second signal response of the second filter. The INMC may select the first filter for impulse noise mitigation when the mean magnitude of the second filter is greater than the mean magnitude of the first filter. The INMC may select the second filter for impulse noise mitigation when the mean magnitude of the first filter is greater than the second filter.Type: ApplicationFiled: July 15, 2013Publication date: November 14, 2013Inventors: Andy Lo, Sugbong Kang