Abstract: The present disclosure relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: The present invention relates to a compensation circuit for providing compensation over PVT variations within an integrated circuit. Using a low voltage reference current source, the compensation circuit generates directly, from an on-chip reference low voltage supply (VDD), a reference current (Iref) that is constant over PVT variations, whereas a detection current (Iz) that is variable over PVT variations is generated by a sensing circuit, which is based on a current conveyor, from a low voltage supply (VDDE?VDD) applied across a single diode-connected transistor (M10) corresponding to a voltage difference between two reference low voltage supplies. Both currents (Iref, Iz) are then compared inside a current mode analog-to-digital converter that outputs a plurality of digital bits. These digital bits can be subsequently used to compensate for PVT variations in an I/O buffer circuit.

Abstract: Apparatus comprising a charge pump (20) with multiple independently regulated outputs (V1, V2) for providing different voltage levels at each of said outputs. The charge pump (20) comprises a low voltage input (12), on/off regulation (30), and at least two charge stages (11, 21) which arc arranged in a cascaded manner. Each charge stage (11, 21) comprises a stage capacitor (16, 26), a switch (S1, S3), and a buffer (15, 25) for pumping a bottom plate of the stage capacitor (16, 26).

Abstract: The electronic circuit comprises a functional module (10), a condition signaling module (20), a reference module (30) and a control circuit (40). The condition signaling module (20) generates an indication signal (Imeas) indicative for PVT conditions local to the functional module. The PVT conditions comprise a set of conditions relevant for a module comprising at least one of a voltage supplied to said module, a temperature within an area occupied by said module and the process conditions relevant for said area The reference module (30) generates a reference signal (Iref) having a value that is substantially independent of said PVT-conditions. The control circuit (40) compares the indication signal (Imeas) and the reference signal (Iref), and for generating a control signal (pvt<1>, . . . , pvt<n>) for the functional module.

Abstract: The invention regards an improved voltage converter with increased current capability. The voltage converter architecture may be configured by software. In the prior art programmable charge pumps have been configured in such a way, that the unused stages were simply short circuited by a decoding logic. According to the invention these stages are used to increase the current capability of the first pumping stage. In particular the result is an increase in current capability of a proposed charge pump device by 10% to 15% without the need of additional parts and within the same area.

Abstract: Driver system (10) for use in connection with a non-linear display array having N×M pixels. The driver system (10) comprises an input for receiving column data representing an image to be displayed, and a row driver designed to sequentially collect the currents of all M pixels of each row of pixels row electrode by row electrode. A gamma correction unit (17) is employed that provides for a gamma correction of the column data. The gamma correction unit (17) is situated at the input side of a display data memory (14) for storing the gamma corrected column data. The driver system (10) further comprises a column driver (24) designed to apply column signals to all M column electrodes in parallel, the column signals being generated in accordance with the gamma corrected column data.