Abstract: A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.

Abstract: An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.

Abstract: An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.

Abstract: A clock divider circuit that adds little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.

Abstract: A method is provided for quickly determining low threshold voltages and high threshold voltages of a test circuit. Specifically, a transformed voltage transfer curve for the test circuit is generated. The maximum and minimum points of the transfer circuit are determined to calculate transformed voltage threshold values. The transformed voltage threshold are transformed to find the desired threshold voltages.

Abstract: Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. In a first mode, the DLL circuit counts and stores a first number of delays necessary to synchronize the two signals. In some embodiments, the circuit also stores a second value representing the number of unit delays in one clock period. In a second mode, the DLL circuit uses the first stored value to add the correct number of unit delays to the input clock signal. In some embodiments, the second stored value is used to generate phased output signals.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.

Abstract: A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. A single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. Further, only one delay line is required to implement the DLL circuit. Therefore, the DLL of the present invention is both quick to “lock in” a clock signal and efficient in the use of hardware resources. Further, the present DLL is very accurate, because the same delay line is used to calculate the necessary additional delay and to generate the output clock signal.

Abstract: A duty cycle correction circuit and method that accept an unsymmetrical input clock signal and provide therefrom an output clock signal having a 50% duty cycle. One circuit according to the invention includes an input clock terminal supplying a input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 180 degrees offset from the input clock signal. The selected clock signal is then combined with the input clock signal in an output clock generator to generate an output clock signal having a 50% duty cycle. In one embodiment, the duty cycle correction circuit includes a delay stage comprising a delay element that can selectively add a half-unit delay to the input clock signal.

Abstract: A clock doubler circuit and method that accept an input clock signal and provide therefrom an output clock signal having twice the frequency of the input clock signal. One circuit according to the invention includes an input clock terminal supplying a input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 90 degrees offset from the input clock signal. The selected clock signal is then combined with the input clock signal in an output clock generator to generate an output clock signal having twice the frequency of the input clock signal. In one embodiment, the clock doubler circuit includes a delay stage comprising a delay element that can selectively add a half-unit delay to the input clock signal.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. Unlike previous circuits and methods, a single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. A circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that provides the necessary additional delay to synchronize the feedback clock signal to the input clock signal.

Abstract: The invention provides an IC driver circuit having an adjustable trip point. The driver circuit automatically adjusts the trip point of the circuit based on the state of the output signal (and thus, by inference, on the state of the input signal), by using first and second switches to couple and decouple secondary pullup and pulldown circuits. In one embodiment, this coupling/decoupling also ensures that the output signal has a shorter rise/fall time than the input signal. Therefore, the output signal reaches a midpoint voltage level (i.e., VCC/2) before the input signal reaches the same level. In a sense, the driver circuit has a negative propagation delay. In a second embodiment, the first and second switches are controlled to ensure low noise-sensitivity, rather than high speed. In another embodiment, the driver circuit can be controlled for either high speed or noise insensitivity.