Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: A circuit for design-for-test (DFT)-mixing and internal clock pulse generation in test and functional modes includes a tristate inverter; a reset circuitry; and a clamp circuitry, where such clamp circuitry is configured for design-for-test (DFT)-mixing. A method for design-for-test DFT-mixing includes: in a test mode, providing a DFT information signal to a circuit; in response to receiving a clock signal at a clamp circuitry, retaining the DFT information signal at the clamp circuitry; and in response to a transition of the clock signal, deactivating the clamp circuitry and generating an internal clock pulse. A method for DFT-mixing includes: in a functional mode, providing, from a tristate inverter, a CTR signal on a critical path of a circuit; in response to an external clock signal, receiving at a logic circuitry coupled to the critical path, at least the CTR signal; and generating, by a first stage of the logic circuitry, an internal clock pulse.

Abstract: A circuit for level-shifting includes a pulse-shaper circuit comprising a first PMOS transistor; and a level-shifting circuit, where the first PMOS transistor is configured to precharge a node on a wordline generation path of the level-shifting circuit. Also, a method of level-shifting includes detecting, at a PMOS transistor of a pulse-shaping circuit, a falling edge of a clock signal; and generating, by the pulse-shaping circuit, a pulse to activate the PMOS transistor to precharge a node on a wordline generation path of a level-shifting circuit. Another circuit for level-shifting includes a first PMOS transistor; and a level-shifting circuitry, where the circuit is configured to generate a pulse on a second voltage domain from a clock signal on a first voltage domain.

Abstract: Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuits comprising memory read output circuitry including a read signal input terminal, a latch, and a combinatorial gate coupled to the read signal input terminal and the latch.

Abstract: Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuits comprising Boolean logic gate circuitry and corresponding voltage level shifting circuitry.

Abstract: A memory instance comprises a bitcell array and peripheral circuitry. A bitcell array power supply provides a fixed voltage for the bitcell array, and a peripheral logic power supply provides a variable voltage for peripheral circuitry. A digital power multiplexer is operable to provide a higher of the bitcell array power supply fixed voltage and the peripheral logic power supply variable voltage to the bitcell array.

Abstract: A clocking scheme for a driving a first signal and a write word line signal to a multi-port memory device, the clocking scheme comprising: a clock configured to control timing of operations within the multi-port memory device, wherein the clocking scheme includes at least two separate clocking phases; and activating the first signal line and the write word line in different clock phases of the clocking scheme, such that the first signal line is activated in a first clock phase and the write word line is activated in a second clock phase.

Abstract: Various implementations described herein are related to a read multiplexer circuit for a multiport register file, comprising: an input stage coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell; a read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node; and a first latch stage comprising second circuitry that provides a third read word line to the first and second storage node of the first set to latch the read from one of the first and second storage nodes.

Abstract: Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

Abstract: Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.

Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: A memory device includes a bitcell array having at least a first plurality of first adjacent bitcell banks and a second plurality of second adjacent bitcell banks. One or more bitcell array input lines are coupled to the bitcell array at a first physical location between the first adjacent bitcell banks. One or more bitcell array output lines are coupled to the bitcell array at a second physical location between the second adjacent bitcell banks. The one or more bitcell array input lines are further coupled from the first plurality of adjacent bitcell banks to the second plurality of bitcell banks at a physical location between the second plurality of adjacent bitcell banks. The one or more bitcell array output lines are further coupled from the second plurality of bitcell banks to the first plurality of bitcell banks at a physical location between the first plurality of bitcell banks.

Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

Abstract: Inrush current in a memory such as SRAM cache may be managed by using one or more integrated delay elements such as inverters, RC delay lines, and the like to significantly slow down power down signal propagation between memory instances in a memory array. The delay in some examples may be between memory instances, while in other examples the delay is also introduced between bitcell arrays within a memory instance. By staggering the power up times of interconnected or chained memory instances, inrush current when powering the memory instances on or resuming from an inactive state may be reduced.

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises: a memory macro unit including: one or more bitcells of one or more bitcell arrays, where a wordline or a bitline is at least partially disposed within a backside metal layer of the memory macro unit. In one implementation, a method comprises: transmitting, by a first wire of wiring, one or more control signals, where the first wire is disposed at least partially within a back-side metal layer. In one implementation, an integrated circuit comprises: a wire configured to transmit one or more control signals, where the wire is disposed at least partially on a back-side metal layer.

Abstract: Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

Abstract: Various implementations described herein are directed to a device having an array of bitcells with a first bitcell disposed adjacent to a second bitcell. The device may have a first wordline coupled to first transistors in the first bitcell, and the device may have a second wordline coupled to second transistors in the second bitcell. Also, the device may have a buried ground line coupled to the first transistors and the second transistors.

Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

Abstract: Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.