Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.

Abstract: A graphical tool for a design of a substrate of an integrated circuit device is described. The graphical tool comprises a processor configured to: display locations of probes for a first plurality of contact elements associated with the substrate; display locations of BGA contact elements associated with the substrate; identify interconnect elements between the first plurality of contact elements and the BGA contact elements; and display connections lines representing the identified interconnect elements. A method of designing a substrate of an integrated circuit device is also described.

Abstract: A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.

Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.

Abstract: Examples of the present disclosure generally relate to a probe head assembly having modular interposer and a test system having the same. In one example, a probe head assembly includes a rigid stiffener plate, a PIB substrate, a bracket, a plurality of interposers disposed in the bracket, a probe card board electrically coupled by a plurality of contact pins disposed through the interposers to the PIB substrate, and a probe card electrically coupled to the probe card board. The PIB substrate, the interposers and the probe card board are sandwiched between the stiffener plate and the probe card.

Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.