Patents by Inventor Aneesh A. Tuljapurkar

Aneesh A. Tuljapurkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11720401
    Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Murali R Iyengar, Karunakara Kotary, Ovais Pir, Sagar C Pawar, Prakash Pillai, Raghavendra N, Aneesh A Tuljapurkar
  • Patent number: 11432421
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Publication number: 20210373833
    Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Sagar Pawar, Prakash Pillai, Ovais Pir, Murali Iyengar, Pannerkumar Rajagopal, Raghavendra N, Aneesh Tuljapurkar
  • Patent number: 10747779
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Publication number: 20200245483
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N.
  • Publication number: 20200225994
    Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Pannerkumar Rajagopal, Murali R. Iyengar, Karunakara Kotary, Ovais Pir, Sagar C. Pawar, Prakash Pillai, Raghavendra N., Aneesh A. Tuljapurkar
  • Patent number: 10653026
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Publication number: 20200125579
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overlocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Application
    Filed: May 30, 2019
    Publication date: April 23, 2020
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Patent number: 10447052
    Abstract: An apparatus system is provided which comprises: a first input/output (I/O) port; a second I/O port; circuitry to generate (i) a first signal at a first voltage level and (ii) a second signal at a second voltage level; and switching circuitry to selectively supply any one of the first signal or the second signal to any one of the first I/O port or the second I/O port.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Anantha Narayanan, Ravindra A. Babu, Aneesh A. Tuljapurkar
  • Publication number: 20190215975
    Abstract: Illustrative examples include a system for coupling a first electronic device to a second electronic device. The first electronic device may include a housing having a first engagement surface and a first magnet array. The first engagement surface may be adapted to receive the second electronic device. The second electronic device may include a second magnet array. An actuator coupled to the first magnet array may move the first magnet array relative to the housing and the second magnetic array, to attractively couple or repulsively de-couple the second electronic device from the first electronic device.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Samarth Alva, Krishnakumar Varadarajan, Yogesh Channaiah, Prakash Pillai, Sagar Pawar, Aneesh Tuljapurkar, Raghavendra N
  • Patent number: 10331200
    Abstract: An apparatus system is provided which comprises: a port to selectively receive a device external to the apparatus; a port control circuitry to selectively supply power to the port; and a controller to selectively turn on or turn off the port.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Anantha Narayanan, Ravindra A. Babu, Aneesh A. Tuljapurkar
  • Patent number: 10318547
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Publication number: 20180293291
    Abstract: Technologies for synchronized overclocking setting between multiple networked computing devices include a master computing device and multiple slave computing devices communicating over a network. The master computing device establishes a connection with the slave computing devices. Establishing the connection may include synchronizing the slave computing devices with a master time clock of the master computing device. The master computing device determines its own overclocking setting and requests overclocking settings from the slave computing devices. The overclocking settings may include processor frequency, processor voltage, or other overclocking parameters. The master computing device determines a best overclocking setting from its own overclocking setting and the overclocking settings received from the slave computing device. The master computing device advertises the best overclocking setting to the slave computing devices. The slave computing devices may implement the best overclocking setting.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: Sagar C. Pawar, Prakash Pillai, Raghavendra N, Aneesh A. Tuljapurkar
  • Publication number: 20180278075
    Abstract: An apparatus system is provided which comprises: a first input/output (I/O) port; a second I/O port; circuitry to generate (i) a first signal at a first voltage level and (ii) a second signal at a second voltage level; and switching circuitry to selectively supply any one of the first signal or the second signal to any one of the first I/O port or the second I/O port.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Inventors: Sagar C. Pawar, Anantha Narayanan, Ravindra A. Babu, Aneesh A. Tuljapurkar
  • Publication number: 20180275738
    Abstract: An apparatus system is provided which comprises: a port to selectively receive a device external to the apparatus; a port control circuitry to selectively supply power to the port; and a controller to selectively turn on or turn off the port.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 27, 2018
    Inventors: Sagar C. Pawar, Anantha Narayanan, Ravindra A. Babu, Aneesh A. Tuljapurkar