Patents by Inventor Aner Arussi

Aner Arussi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device
    Patent number: 8351263
    Abstract: Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count.
    Type: Grant
    Filed: July 19, 2009
    Date of Patent: January 8, 2013
    Assignee: Infinite Memory Ltd.
    Inventor: Aner Arussi
  • Method of handling reference cells in NVM arrays
    Patent number: 8248855
    Abstract: A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 21, 2012
    Assignee: Infinite Memories Ltd.
    Inventors: Eli Lusky, Aner Arussi, Amir Gabai
  • METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS
    Publication number: 20120206962
    Abstract: A memory chip includes memory cells storing data to be read; at least one reference cell having a reference cell current level and a reference gate voltage adjuster to adjust, for each reference cell, a reference gate voltage level to compensate for a shift of the reference cell current level from an original current level.
    Type: Application
    Filed: April 4, 2012
    Publication date: August 16, 2012
    Applicant: INFINITE MEMORIES LTD.
    Inventors: Eli LUSKY, Aner ARUSSI, Amir GABAI
  • METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS
    Publication number: 20110222338
    Abstract: A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 15, 2011
    Inventors: ELI LUSKY, Aner Arussi, Amir Gabai
  • METHOD CIRCUIT AND SYSTEM FOR OPERATING AN ARRAY OF NON-VOLATILE MEMORY ("NVM") CELLS AND A CORRESPONDING NVM DEVICE
    Publication number: 20100290287
    Abstract: Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count.
    Type: Application
    Filed: July 19, 2009
    Publication date: November 18, 2010
    Inventor: Aner Arussi