Abstract: A current-mode-control circuit for a switching regulator is provided. The circuit includes a first transistor coupled to a power supply voltage, a second transistor, and an inductor. The circuit further includes a slope compensation generation circuit coupled to the output of the current control circuit through a feedback loop, the slope compensation generation circuit generating a slope compensation current related to the output voltage, an inductor current sensing circuit coupled to the first transistor and the second transistor, and configured to calculate a current through the inductor and output a inductor sense current, and a pulse-width modulation control circuit coupled to the slope generation circuit and the inductor current sense circuit, the pulse-width modulation control circuit receiving the output of the current control circuit, the slope compensation current and the inductor sense current as inputs.

Abstract: A current-mode-control circuit for a switching regulator is provided. The circuit includes a first transistor coupled to a power supply voltage, a second transistor, and an inductor. The circuit further includes a slope compensation generation circuit coupled to the output of the current control circuit through a feedback loop, the slope compensation generation circuit generating a slope compensation current related to the output voltage, an inductor current sensing circuit coupled to the first transistor and the second transistor, and configured to calculate a current through the inductor and output a inductor sense current, and a pulse-width modulation control circuit coupled to the slope generation circuit and the inductor current sense circuit, the pulse-width modulation control circuit receiving the output of the current control circuit, the slope compensation current and the inductor sense current as inputs.

Abstract: Embodiments of the present invention provide a random number generating apparatus, including a first level sampling module and a second level sampling module. The first level sampling module includes a first oscillator, a second oscillator and a first sampler capable of sampling the first oscillating signal with the second oscillating signal to generate a first output signal. The second level sampling module includes a voltage-controlled oscillator capable of generating a voltage-controlled oscillating signal by using the first output signal as a control voltage, a third oscillator capable of generating a third oscillating signal, and a second sampler, capable of sampling the third oscillating signal with the voltage-controlled oscillating signal and generating random numbers. The first level oscillator sampling provides a random control voltage for the second level oscillator sampling, therefore improving the randomicity of the second level oscillator sampling as well as the random number generating rate.

Abstract: In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and adjusting a current level of a charge pump pulse by an incremental amount to achieve a fractional portion of a new loop bandwidth. The charge pump pulse is filtered to generate the frequency adjustment signal and the frequency spike reduction process is repeated until the new loop bandwidth is achieved.

Abstract: In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and adjusting a current level of a charge pump pulse by an incremental amount to achieve a fractional portion of a new loop bandwidth. The charge pump pulse is filtered to generate the frequency adjustment signal and the frequency spike reduction process is repeated until the new loop bandwidth is achieved.

Abstract: Embodiments of the present invention provide a random number generating apparatus, including a first level sampling module and a second level sampling module. The first level sampling module includes a first oscillator, a second oscillator and a first sampler capable of sampling the first oscillating signal with the second oscillating signal to generate a first output signal. The second level sampling module includes a voltage-controlled oscillator capable of generating a voltage-controlled oscillating signal by using the first output signal as a control voltage, a third oscillator capable of generating a third oscillating signal, and a second sampler, capable of sampling the third oscillating signal with the voltage-controlled oscillating signal and generating random numbers. The first level oscillator sampling provides a random control voltage for the second level oscillator sampling, therefore improving the randomicity of the second level oscillator sampling as well as the random number generating rate.