Patents by Inventor Angélique Denise RALEY

Angélique Denise RALEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8906760
    Abstract: Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 9, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Angelique Denise Raley
  • Publication number: 20140120728
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 1, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Angelique Denise RALEY, Takuya MORI, Hirota OHTAKE
  • Patent number: 8664125
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Angelique Denise Raley, Takuya Mori, Hiroto Ohtake
  • Publication number: 20130260561
    Abstract: Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 3, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Alok Ranjan, Angelique Denise Raley
  • Publication number: 20130164940
    Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Angélique Denise RALEY, Takuya MORI, Hiroto OHTAKE