Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include generating primitive circuit structures using the material or process changes; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a digital system based on the compact models; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include generating primitive circuit structures using the material or process changes; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a digital system based on the compact models; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include translating the material or process change into a database of characteristics; generating primitive circuit structures using the database of characteristics; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a lite version of standard cells; generating a digital system based on the lite version of the standard cells; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include translating the material or process change into a database of characteristics; generating primitive circuit structures using the database of characteristics; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a lite version of standard cells; generating a digital system based on the lite version of the standard cells; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.