Abstract: Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.

Abstract: Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

Abstract: In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.