Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A system and method of wireless power transfer using a power converter with a bypass mode includes a power converter. The power converter includes a pulsed switch, a capacitor configured to supply a drive voltage to the pulsed switch, a first circuit configured to charge the capacitor when the power converter operates in a switched mode of operation, and, a second circuit configured to charge the capacitor when the power converter operates in a bypass mode of operation.

Abstract: A temperature-compensated voltage comparator (301) that compares first and second input voltages includes first and second bipolar junction transistors (BJTs) (221 and 222) that convert the first and second input voltages to first and second input currents, respectively. The first and second BJTs share a same thermal environment and their currents are dependent upon temperature. A temperature-compensating circuit (350), which includes a zero thermal coefficient reference (419), generates a logarithmic temperature-compensating factor that compensates for temperature dependency of the first and second BJTs. The temperature-compensating circuit receives one of the input currents, and outputs a temperature-compensated current that is said input current multiplied by the logarithmic temperature-compensating factor. The temperature-compensating circuit shares a thermal environment with the first and second BJTs.

Abstract: A temperature-compensated voltage comparator (301) that compares first and second input voltages includes first and second bipolar junction transistors (BJTs) (221 and 222) that convert the first and second input voltages to first and second input currents, respectively. The first and second BJTs share a same thermal environment and their currents are dependent upon temperature. A temperature-compensating circuit (350), which includes a zero thermal coefficient reference (419), generates a logarithmic temperature-compensating factor that compensates for temperature dependency of the first and second BJTs. The temperature-compensating circuit receives one of the input currents, and outputs a temperature-compensated current that is said input current multiplied by the logarithmic temperature-compensating factor. The temperature-compensating circuit shares a thermal environment with the first and second BJTs.

Abstract: A technique of detecting an open integrated circuit (IC) pin includes selectively coupling a first open detect circuit, which includes a first inverter having a first threshold, to the IC pin. Next, a first logic state at an output of the first inverter is determined. Then, based upon the first logic state, it is determined whether the IC pin is open or whether it is indeterminate as to whether the IC pin is open. When it is indeterminate as to whether the IC pin is open, based on the first logic state, a second open detect circuit is selectively coupled to the IC pin. The second open detect circuit includes a second inverter having a second threshold (the first threshold is greater than the second threshold). A second logic state at an output of the second inverter is then determined. Finally, based upon the first and second logic states, it is determined whether the IC pin is open.

Abstract: A technique of detecting an open integrated circuit (IC) pin includes selectably coupling a first open detect circuit, which includes a first inverter having a first threshold, to the IC pin. Next, a first logic state at an output of the first inverter is determined. Then, based upon the first logic state, it is determined whether the IC pin is open or whether it is indeterminate as to whether the IC pin is open. When it is indeterminate as to whether the IC pin is open, based on the first logic state, a second open detect circuit is selectably coupled to the IC pin. The second open detect circuit includes a second inverter having a second threshold (the first threshold is greater than the second threshold). A second logic state at an output of the second inverter is then determined. Finally, based upon the first and second logic states, it is determined whether the IC pin is open.