Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metalization reroute from the user-selected bond pads and vias is applied. The inactive surface of the wafer may be back thinned if desired. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: There is disclosed an efficient, cost effective production method to bond layers of electronic devices into an integral stack, or for joining electronic devices to other devices or substrates with use of an adhesive material, preferably an appropriate polyimide, to provide, in effect, a two-stage bonding process. In the first stage, the electronic device is coated, preferably at the wafer level, with a liquid solution of the adhesive material, the coated device is heated to remove solvent, forming a dry adhesive coating of sufficient thickness to fill all spaces between metal traces on the electronic device. Coated wafers can be stacked and bonded, or preferably diced to yield individual chips, which are cut and stacked in a suitable fixture, and heat and pressure are applied in a second stage, to cause viscous flow of the adhesive, filling all voids, and to cure the adhesive, creating an integral, adhesively bonded stack.

Abstract: A method and product are disclosed in which multiple solder bumps on a first planar surface are guided into engagement with terminals on a second planar surface by means of holes formed (by a photolithographic process) in a dielectric layer, which has been added to the second surface to provide the holes (or sockets) through which the solder bumps (or plugs) extend. The perforated (hole-providing) layer may be formed of one of several materials. The preferred perforated layer material is a photo-definable polyimide, which is hardened by heating after the holes have been formed. Small solder bumps may be formed inside the holes on the second surface, in order to facilitate bonding between the solder bumps on the first surface and the terminals on the second surface.

Abstract: A method for fabricating stacks of IC chips into modules providing high density electronics. A relatively large number of layers are stacked, and then integrated by curing adhesive applied between adjacent layers. A large stack is formed, various processing steps are performed on the access plane face of the large stack, and then the large stack is segmented to form a plurality of smaller, or short, stacks. Means are provided for causing separation of the larger stack into smaller stacks, without disturbing the adhesive which binds the layers within each small stack.

Abstract: An improved method of forming metal contact bumps for infrared detector array includes depositing a thick layer of positive organic photoresist, and exposing the entire layer to light. A second, substantially thinner layer of photoresist is then applied, and exposed with a pattern of light corresponding to the contact bumps desired. The photoresist is developed to resolve the pattern in the top thin film, and the underlying thick resist is isotropically developed down to the substrate surface and under a portion of the remaining unexposed top layer. the metal to form the contact bumps is then deposited, preferably by evaporative deposition. The overhanging edges of the top layer of photoresist prevent continuous metal step coverage between the surface of the photoresist layer and the bumps formed on the substrate surface in the cavity. The remaining photoresist is then dissolved, and the metal deposited on the surface of the second layer is readily removed.