Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Abstract: Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated.

Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.

Abstract: Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.

Abstract: Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified.

Abstract: Provided is a method of testing a logic device. The method includes comparing a first test pattern provided at an input of a first chain of logic device sub-modules with an output from the first chain to determine first type failures and comparing a second test pattern provided at an input of a second chain of logic device sub-modules with an out from the second chain to determine second type failures. An occurrence of one of the first type failures renders the logic device inoperable. An occurrence of the second type of failures is tolerated.

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.