Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

Abstract: Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.

Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

Abstract: A method for generating a software-based self-test in an integrated circuit includes extracting constraints for corresponding instructions for the integrated circuit, modeling the constraints for a plurality of timeframes and performing constrained test pattern generation on the integrated circuit using the models. An automatic test pattern generation method for an AC fault in an integrated circuit includes identifying a current desired condition for triggering the AC fault, determining whether the current desired condition is feasible, and identifying a subsequent desired condition for triggering the AC fault if the current desired condition is not feasible. The method further includes determining whether the subsequent desired condition for triggering the AC fault is feasible, and searches for test vectors for realizing the current desired condition or subsequent desired condition which is determined to be feasible.

Abstract: At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.

Abstract: A method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault will degrade the circuit performance. Identification and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely affect more than one path and these defects can be detected only by analyzing multiple affected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). The methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) reduce or prune the combination of paths that can never belong to any primitive fault.