Abstract: Methods, systems, and computer readable media can be operable to facilitate the recovery of a failed data path. A determination may be made that one or more channels have become unavailable to a central device. The central device may identify an opportunity to attempt to recover the one or more unavailable channels, the opportunity being based upon a waiting period, time-of-day, device activity, or other parameter. A communication interface associated with the central device may be re-initialized so that the central device can attempt to recover the one or more unavailable channels.

Abstract: Methods, systems, and computer readable media can be operable to facilitate the recovery of a failed data path. A determination may be made that one or more channels have become unavailable to a central device. The central device may identify an opportunity to attempt to recover the one or more unavailable channels, the opportunity being based upon a waiting period, time-of-day, device activity, or other parameter. A communication interface associated with the central device may be re-initialized so that the central device can attempt to recover the one or more unavailable channels.

Abstract: Switch and MAC layer components are located at a headend and PHY layer components for connecting a plurality of end-user devices are located remotely at nodes. Using SSMII technology, MAC layer ports can communicate with an equal number of PHY layer interface ports serially. Thus, the MAC layer connects to the PHY layer via fiber links, a separate link being used for each direction of traffic data flow. Information data is encoded along with a frame sync signal and a clock signal into a serial stream for transmission across the network. The serial stream is decoded at the other end, and the frame sync signal is extracted to provided timing functionality. This allows full duplex operation with the MAC layer separated from the PHY layer at distances greater than a few inches. Also, user device status may be monitored at the single switch location.

Abstract: Wireless interface nodes couple to a wireless protocol controller over an HFC network. The wireless controller, located at the head end, interfaces the CMTS with the HFC. Thus, a conversion between standard packets and wireless protocol packets occurs; packets are transmitted/received at standard HFC frequencies to/from the wireless interface nodes. The wireless nodes upconvert downstream signals to a wireless frequency and transmit same from an antenna. Upstream signals received from wireless user devices at wireless frequencies are downconverted at the wireless node to HFC upstream frequencies. When downstream packet signals from the head end are detected, upstream signal processing at the node is disabled. If this results in loss of preamble bits, additional preamble bits may be added at the head end. Upstream processing may be disabled unless upstream packets are present. DOCSIS in-band signaling may be used to communicate control information between the head end and the wireless nodes.

Abstract: A user-device combines a DOCSIS modem and an upconverter radio circuit to convert upstream traffic signals from the modem output from the 5-42 MHz range to the Lower 700 MHz Band. This upconverted signal is amplified and transmitted from an antenna, which may be located external to the device, or inside the device. A local oscillator provides the upconverter radio circuit with a periodic signal having a frequency that is sufficiently different from the combined signal from the upconverter so that filtering the periodic signal from the combined signal does not require as precise tuning as if the carrier frequencies of the periodic signal and the combined signal were closer in frequency. A diplex filter, with the antenna electrically on one side and the upconverter radio circuit and a downstream amplifier on the other, separates upstream and downstream traffic from a single antenna connection.

Abstract: A direct broadcast satellite system delivers video content to a subscriber and a CATV network is used to simultaneously provide data services to the same subscriber. Since the CATV system is not used to deliver video/television programming channels, these same channels can be used to transport downstream and upstream data signals. To provide upstream performance and immunity to noise, upstream data traffic signals from a subscriber's cable modem are upconverted for transmission by channels having center frequencies higher than 42 MHz.

Abstract: Switch and MAC layer components are located at a headend and PHY layer components for connecting a plurality of end-user devices are located remotely at nodes. Using SSMII technology, MAC layer ports can communicate with an equal number of PHY layer interface ports serially. Thus, the MAC layer connects to the PHY layer via fiber links, a separate link being used for each direction of traffic data flow.

Abstract: A remote transmitter and receiver for remotely controlling multimedia devices served by a converged multi-media portal for coupling a plurality of multi-media signals carried on a single network medium to a plurality of corresponding multi-media devices. Each device is served by a multi-media processing modules, which receives a multi-media signal from a network interface module and routes at least one multi-media signal to a corresponding multi-media device. Each module may comprise a remote control receiver. Alternatively, a separate control module that serves other multi-media processing modules may comprise a single receiver.

Abstract: A network interface card for a personal computer includes a controller chip and a programmable logic array that is coupled at its output terminals to the bus pull-up resistors, or to dedicated terminals of the controller chip for establishing different configurations for the controller chip on the interface card. A rotary, ten position binary coded decimal switch is coupled across the inputs of the programmable logic array. Each position of the switch establishes a different configuration for the controller. The arrangement eliminates the need for manual switches and movable jumpers for configuring the network interface card controller chip.

Abstract: A broadband communications network includes a plurality of stations interconnected through selected forward and reverse channels by a network translator. Each station continuously monitors the forward channel for detecting the presence or absence of a forward channel carrier. A given station is allowed to transmit a data packet as modulation of the reverse channel carrier only after the expiration of a predetermined time interval during which no carrier is detected on the forward channel. By establishing the predetermined time interval for each respective station in inverse relation to the distance of the station from the network translator, a synchronized transmission time base as well as equalized station access is achieved for improving network performance.

Abstract: A communications system includes one or more channels each comprising a plurality of LANs having multiple stations. The LANs of a particular channel are interconnected by a bridge interface, the respective bridge interfaces being connected by a backbone network. Each station is capable of transmitting a data packet including a header having either a 0 or 1 bridge flag, LAN stations being responsive only to data packets having a 0 bridge flag and bridge interfaces only to packets having a 1 bridge flag. Intra-LAN communications are thus effected by data packets having headers with 0 bridge flages while inter-LAN communications are effected by transmitting a packet with a 1 bridge flag from a source station which is coupled to the destination station by the bridge which also changes the bridge flag to 0. A special "broadcast" header is used to effect communications when the LAN or channel of the destination station is unknown.

Abstract: The present invention is a circuit for controlling the sampling of plurality of channels in an electronic organ having multiplexed keying. The channels having information signals at a particular time period is sensed and used to address a memory. The memory has stored a plurality of sequences of digital signals for controlling the multiplexing and demultiplexing operations of the organ. Only those channels containing information signals are sampled which accordingly increases the sampling rate which increases the frequency of the harmonic component of the square wave signals that can be passed by the system and the distortion caused by aliasing of harmonics is diminished.

Abstract: The present invention is a differential sampling circuit for improving the signal to noise ratio by eliminating d.c. level distortion in square wave signals used as components for forming a stairstep or bright wave signal in an electronic organ having multiplexed keying. The multiplexed drawbar signals for even footages at both sides of a sampling resistor are demultiplexed, applied to a sample and hold circuit and applied as inputs to a differential amplifier to cancel any fluctuations of the d.c. signal component.

Abstract: The present invention is a chord teaching system and method which assists the organist in learning musical chords. The system functions in several different modes and the various modes are selected by the learning organist. The chord teaching system enables the learning organist to select a chord without demonstrating any knowledge of the correct finger position on the keyboard of the organ necessary to play the chord. The system, depending upon the mode of operation, plays the chord selected and indicates to the learning organist the key corresponding to the root note of the selected chord or indicates to the organist the keys corresponding to the notes of the selected chord or enables the organist to depress the keys that the organist believes form the selected chord and indicates a correct response if the organist depresses the proper key and indicates the correct keys that form the notes of the chord if the response is incorrect.

Abstract: A harmony signal generating system for an electronic organ comprises a plurality of integrated circuit chips which each receive upper and lower manual keying signals for two consecutive organ notes. A first read only memory (ROM) generates octave identify signals to designate the octave of an active upper manual note. A second ROM generates octave select signals which are combined with the octave identify signals in a third ROM to generate the harmony signals which comprise the lower manual chording signals played through the upper manual within a twelve note range above an active upper manual note and an upper manual note which is one octave above the active upper manual note. The octave identify signals are provided in parallel among the chips from the chip having the lowest active upper manual letter note. Upper manual active signals generated in response to the upper manual keying signals are connected in series among the chips to select the appropriate chip.

Abstract: A multiplexed electronic organ utilizing a plurality of integrated circuit chips, each chip time division multiplexing selected keying envelope time constant signals from a switched capacitor time constant generator for two alphabetic notes over the entire frequency range of a spinet or for one alphabetic note over the entire frequency range of the manuals and pedals of a console organ. The same integrated circuit chip is used for both spinet or console organs. Each chip contains a multiplexer circuit which isolates the multiplexed keying envelope output signals from the time constant generator and includes as a coupling means a plurality of switching element arranged into groups. Some of the groups are interconnected to provide the keying envelope time constant signal normally intended for one frequency range to the output associated with a different frequency range.

Abstract: An electronic reverberation system for use in an electronic musical instrument comprises a random access memory wherein two or more time delay channels are defined by address allocation in a controller circuit. An input analog signal is converted to digital signals by an analog-to-digital converter and the digital signals are processed by the controller into the time delay channels. The channels defined in the random access memory are of differing lengths which can be changed by switch settings. The controller sequentially retrieves stored digital data words from the random access memory channels in seriatum and couples each data word to a digital-to-analog converter. The analog output signal from the digital-to-analog converter is delayed in time by varying amounts due to the length of the channels in the random access memory. A portion of the delayed analog output signal contained in each channel is mixed with the input analog signal to produce a combined signal.

Abstract: A dynamic one finger chording system with memory is connected in parallel relationship to the d.c. keying lines connecting a select number of keys of the manual to a standard keyer circuit of an electronic organ. The one finger chording system scans each keying line until a line with a d.c. level voltage signal corresponding to a manually depressed key is detected. An identification of the detected line is used as the address to a read only memory. In response to the address, the read only memory provides a preselected d.c. level output signal which through appropriate output circuits drives respective keying lines. Thus one keying line has a d.c. level signal due to the manual depression of a key and a predetermined number of keying lines have a d.c. level signal due to the output signal from the one finger chording read only memory. The same keyer circuit that is used during normal playing now provides a chord output signal.

Abstract: A chord recognition system for an electronic musical instrument, namely an electronic organ. A shift register receives data information from the keying lines of selected playing keys. The pattern of the received data is compared against selected normalized chord patterns in a program logic array to determine if the note input sequence is in a known musical relationship such as major, minor, minor sixth, seventh or others. A chord logic circuit receives the information from the programmed logic circuit and further reduces the information to output signals indicating a major, minor, or seventh chord and a pattern found signal. If no chord pattern is detected in the input data sequence, the register shifts the data on its first input line to its last input line and all other data is transferred downward accordingly. A counter sequences at each shift of the data input information. The shifted data is now compared in the programmed logic array as described above.

Abstract: A pedal teaching system for an electronic musical instrument, specifically an electronic organ. In the rehearse mode of operation the system rhythmically energizes selected ones of a plurality of lights mounted above the pedal clavier to illustrate which pedals form a bass note accompaniment routine for a specific group of keys depressed by the organist and automatically sounds the bass note routine. In the perform mode of operation the system rhythmically energizes selected ones of the plurality of lights to illustrate which pedals form the bass note accompaniment routine and disables the automatic bass note musical output routine so that the organist must physically depress the actual pedals to provide the bass note accompaniment.