Patents by Inventor Angelo Bovino
Angelo Bovino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8572361Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.Type: GrantFiled: March 15, 2011Date of Patent: October 29, 2013Assignee: Micron Technology, Inc.Inventors: Angelo Bovino, Roberto Ravasio, Rino Micheloni
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Publication number: 20110167206Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.Type: ApplicationFiled: March 15, 2011Publication date: July 7, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Angelo Bovino, Roberto Ravasio, Rino Micheloni
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Patent number: 7937576Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.Type: GrantFiled: July 28, 2006Date of Patent: May 3, 2011Assignee: Micron Technology, Inc.Inventors: Angelo Bovino, Roberto Ravasio, Rino Micheloni
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Patent number: 7581153Abstract: A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.Type: GrantFiled: September 8, 2005Date of Patent: August 25, 2009Inventors: Rino Micheloni, Roberto Ravasio, Angelo Bovino, Vincenzo Altieri
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Patent number: 7382660Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.Type: GrantFiled: July 20, 2006Date of Patent: June 3, 2008Assignees: STMicroelectronics S.R.L., Hynix Semiconductor Inc.Inventors: Angelo Bovino, Vincenzo Altieri, Roberto Ravasio, Rino Micheloni, Mario De Matteis
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Patent number: 7362616Abstract: A non-volatile memory device is proposed.Type: GrantFiled: July 28, 2006Date of Patent: April 22, 2008Assignee: STMicroelectronics S.r.l.Inventors: Angelo Bovino, Rino Micheloni, Roberto Ravasio
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Patent number: 7336538Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.Type: GrantFiled: July 28, 2006Date of Patent: February 26, 2008Assignee: STMicroelectronics S.r.l.Inventors: Luca Crippa, Chiara Missiroli, Roberto Ravasio, Rino Micheloni, Angelo Bovino
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Publication number: 20070047299Abstract: Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bit requires a preliminary reading to detect whether the first bit has been modified, performing a first writing step to bring the cell to a third threshold voltage if the first bit has been modified and performing a second writing step to bring the selected cell to a fourth threshold voltage different from the third threshold level if the first bit has not been modified. For increasing reading and program reliability, during preliminary reading of the second portion a reading result is forced to correspond to the first threshold level.Type: ApplicationFiled: July 20, 2006Publication date: March 1, 2007Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.Inventors: Angelo Bovino, Vincenzo Altieri, Roberto Ravasio, Rino Micheloni, Mario De Matteis
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Publication number: 20070038852Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.Type: ApplicationFiled: July 28, 2006Publication date: February 15, 2007Applicant: STMicroelectronics S.r.l.Inventors: Angelo Bovino, Roberto Ravasio, Rino Micheloni
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Publication number: 20070030735Abstract: A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell.Type: ApplicationFiled: July 28, 2006Publication date: February 8, 2007Inventors: Luca Crippa, Chiara Missiroli, Roberto Ravasio, Rino Micheloni, Angelo Bovino
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Publication number: 20070030730Abstract: A non-volatile memory device is proposed.Type: ApplicationFiled: July 28, 2006Publication date: February 8, 2007Inventors: Angelo Bovino, Rino Micheloni, Roberto Ravasio
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Publication number: 20060059406Abstract: A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.Type: ApplicationFiled: September 8, 2005Publication date: March 16, 2006Applicants: STMicroelectronics S.r.l., Hynix Semiconductor Inc.Inventors: Rino Micheloni, Roberto Ravasio, Angelo Bovino, Vincenzo Altieri