Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

Abstract: Subject matter disclosed herein relates to an erasable memory device, and more particularly to a securely erasable flash memory device.