Abstract: An incoming data stream in the output of a demodulator and its derivative in the output of a differentiator are passed by respective sampling gates to a pair of equalizers operating by recursive filtration. The optimized data pulses issuing from the first equalizer are quantized and, after storage in a shift register, are algebraically combined in a first adder with a reference signal x from that equalizer representing the vector sum of weighted data pulses from a succession of N preceding clock cycles; a resulting error signal e.sub.n is delivered to three cumulative multipliers forming part of three feedback loops which supply an optimized phase signal .zeta. to the demodulator, an optimized timing signal .tau. to the sampling gates and an optimized gain coefficient K to the equalizers. These three multipliers respectively receive the reference signal x from the first equalizer, an optimized differential signal dx/d.tau. from the second equalizer and an updating signal z from the first equalizer.

Abstract: Incoming data pulses from a transmission channel are differentially combined with feedback pulses from the downstream end of a cascade of (N-1) delay networks to form an updating signal fed in parallel to a first set of multipliers for weighting with respective coefficients b.sub.1 - b.sub.N.sub.-1. These multipliers deliver optimized signal components to the inputs of respective delay networks of the cascade, through the intermediary of adders in each instance except for the first delay network at the upstream end; a further adder downstream of the last delay network may superimpose the updating signal, weighted with a coefficient b.sub.N by an N.sup.th multiplier of the first set, upon the feedback pulse issuing from the last delay network to generate an additional signal component. At least the more significant signal components, from the inputs of the delay networks located further upstream in the cascade, are weighted in a second set of multipliers with respective coefficients a.sub.1, a.sub.2 etc.

Abstract: Incoming data pulses from a transmission channel are differentially combined with weighted data pulses from preceding cycles to form an updating signal fed in parallel to a multiplicity of weighting circuits for digital multiplication with respective coefficients K.sub.1 - K.sub.N, the output signals from these weighting circuits being synthesized in staggered relationship to form a composite signal fed to a quantizing decoder. The weighting coefficients K.sub.1 - K.sub.N are continuously modified under the control of an error signal derived from a locally generated reference code during an acquisition phase and from the decoder output during an operating phase.