Abstract: A current limiting system for a direct-current-to-direct-current (DC-to-DC) converter includes a current generator, voltage control circuitry, and a filter capacitor. The current generator is electrically coupled between an energy source node and a converter input power node, and the current generator is configured to limit a magnitude of a direct current (DC) component of current flowing through the current generator to a predetermined maximum value and to attenuate one or more alternating current (AC) components of current flowing through the current generator. The voltage control circuitry is electrically coupled to the current generator and is configured to generate a control signal for controlling operation of the DC-to-DC converter to regulate a magnitude of a voltage across the current generator. The filter capacitor is electrically coupled between the converter input power node and a reference node.

Abstract: A power management device includes a first input port configured to be electrically coupled to an energy source, a second input port configured to be electrically coupled to a capacitor, a first output port configured to be electrically coupled to a first load, and a direct-current-to-direct-current (DC-to-DC) converter. The DC-to-DC converter is configured to (a) charge the capacitor from energy of the energy source and (b) provide energy to the first output port at least partially using energy stored in the capacitor. The energy source includes, for example, a battery.

Abstract: Aspects of the disclosure relate to a device that includes a plurality of light sources comprising a first light source and a second light source configured to emit electromagnetic radiation. The device may be configured to determine to perform a first set of measurements on the subject within a time window, wherein the first set of measurements comprise a first measurement performed with the first light source using a first optimal voltage and a second measurement performed with the second light source using a second optimal voltage, wherein the first measurement and the second measurement are performed in a contiguous sequence within the time window, and wherein the first optimal voltage is different from the second optimal voltage. The device may be further configured to apply the first optimal voltage to the first light source and apply the second optimal voltage to the second light source.

Abstract: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.

Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.

Abstract: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.

Abstract: A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the read content to the test datum, and writing thereinto the test datum complement; c) accessing each memory element according to a second scanning sequence, reading a content thereof, comparing the read content to the test datum complement, and writing thereinto the test datum; d) accessing each memory element according to the second scanning sequence, reading a content thereof, comparing the read content to the test datum, writing thereinto the test datum complement, and reading again the content thereof and comparing the read content to the test datum complement.

Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.