Abstract: A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.

Abstract: An integrated circuit has a plurality of signal paths, at least one of which has a delay cell. The delay cell has an input terminal for receiving an signal from the signal path, and a plurality of delay paths for generating a corresponding plurality of delayed signals delayed by different delays from the input signal. At least one of the delay paths employs two different-delay subpaths coupled in parallel to provide a delayed signal delayed by an interpolated delay. A multiplexer (MUX) of the delay cell provides one of the delayed signals as an output signal to the signal path based on a control input signal applied to the multiplexer.

Abstract: Apparatus and process for allowing a user to selectively disable all or a portion of the manual controls, e.g., the keypad and/or other buttons (including switches, keys, on-hook button, and/or other buttons) of customer premises equipment. The customer premises equipment includes a button disabling module which allows subsequent control signals relating to the particular keys or buttons which have been disabled to be essentially ignored. Thus, for instance, if an on-hook button is inadvertently depressed while the on-hook button has been disabled by the button disabling module, the telephone line interface of the telephone will not signal the termination of the telephone call to the central office. The manual controls of the customer premises equipment can be disabled by the user in any of a number of different ways.

Abstract: An improved complementary logic driven level shifter which typically improves switching speed over the prior art diode-type circuit, and allows for symmetrical delays for both high-to-low and low-to-high transitions, thus reducing settling times. The complementary CMOS and not-CMOS inputs to the level shifter are applied to the gates of a pair of P-channel FETs and also to the gates of a pair of N-channel FETs. The sources of the P-channel FETs are coupled to a current source. The drain of each P-channel FET is coupled to the drain of the N-channel FET to which its gate is coupled, and also to the anode of a diode. The cathodes of the two diodes, and the sources of the N-channel FETs are coupled together to the anode of a grounded cathode diode. The output SELECT is the common connection point of the drains of the FETs whose gates are coupled to not-CMOS, and the complementary not-SELECT output is the drains of the FETs whose gates are coupled to CMOS.

Abstract: A circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed. The stabilization circuit is formed to generate a reference current that is proportional to a reference capacitance C.sub.S and the thermal voltage V.sub.T. The reference current is ultimately mirrored (as the bias current) into the bipolar devices which determine the gm within the analog circuit. Since the transconductance gm of a bipolar device can be expressed as collector current, I.sub.C, divided by V.sub.T, the thermal voltage factor of the bias current itself will "cancel" the thermal voltage factor present in the transconductance. The effects related to the remaining variable, the capacitance, will be eliminated as long as the reference capacitance is formed to "track" the analog circuit capacitance by using similar types of capacitance to implement both capacitors and forming both the stabilization circuit and the analog circuit on the same silicon chip.

Abstract: A receiver for decoding passband signal pulses transmitted in accordance with a M-ARY phase shift keying modulation scheme, comprises a multiphase sampler for sampling received passband signal pulses in the passband frequency range so as to generate a plurality of digital words corresponding to the sampled passband signal pulses, such that each digital word represents the phase of each sampled passband signal pulse. A phase reference register or other storage device is coupled to the multiphase sampler for storing one of the digital words as a phase reference such that other digital words generated by the multiphase sampler are compared with the digital word corresponding to the phase reference for decoding the passband signal pulses.

Abstract: A logic gate arrangement having a master gate or section for controlling the logic threshold voltage of slave gates responsive to the master. Both the master and slave gates have two opposite conductivity type transistors disposed in combination with a logic function circuit. The transistors have a common gate connection to a control input. Varying the voltage on the control input varies the logic threshold voltage of the gate. The logic function in the master gate is typically an inverter, with input and output connected together and driving the control inputs of the slave gates. The logic function of the slave gates may be a variety of different logic functions. The logic threshold voltage of the slave gates is substantially the same as a voltage applied to the control input of the master gate.