Abstract: An oscillator circuit includes a comparator having first and second inputs, the first input configured to be coupled to a reference voltage. The oscillator circuit also includes a capacitor and a first current source. The capacitor is coupled between the second input and ground. The first current source is coupled between a supply voltage terminal and the capacitor. The first current source is configured to generate a current to the capacitor that is proportional to absolute temperature.

Abstract: An oscillator circuit includes a comparator having first and second inputs, the first input configured to be coupled to a reference voltage. The oscillator circuit also includes a capacitor and a first current source. The capacitor is coupled between the second input and ground. The first current source is coupled between a supply voltage terminal and the capacitor. The first current source is configured to generate a current to the capacitor that is proportional to absolute temperature.

Abstract: An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the resistor terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.

Abstract: An integrated circuit includes a first field effect transistor (FET) and a second FET formed in or over a semiconductor substrate and configured to selectively conduct a current between a first circuit node and a second circuit node. The first FET has a first source, a first drain and a first buried layer all having a first conductivity type, and a first gate between the first source and the first drain. The second FET has a second source, a second drain and a second buried layer all having the first conductivity type, and a second gate between the second source and the second drain. A first potential between the first source and the first buried layer is configurable independently from a second potential between the second source and the second buried layer.

Abstract: In a switching regulator driver, a sense circuit has a transistor current input and a sense circuit output. A logic circuit has a logic circuit input and first and second outputs. The logic circuit input is coupled to the sense circuit output. A counter has a counter clock input, a counter control input and a counter output. The counter clock input is coupled to the first output. The counter control input is coupled to the second output. The counter is configured to provide a count value at the counter output. A programmable drive strength circuit has a drive strength circuit input and a transistor control output. The drive strength circuit input is coupled to the counter output. The programmable drive strength circuit is configured to adjust a drive current at the transistor control output based on the count value.

Abstract: A current mirror circuit includes a first current mirror transistor, a second current mirror transistor, and a bias circuit. The first current mirror transistor includes a gate and a drain. The second current mirror transistor includes a gate coupled to the gate of the first current mirror transistor. The first current mirror transistor and the second current mirror transistor are low threshold voltage transistors. The bias circuit is coupled to the gate and the drain of the first current mirror transistor. The bias circuit is configured to bias the first current mirror transistor to operate in a saturation mode when a threshold voltage of the first current mirror transistor is a negative voltage.

Abstract: An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the resistor terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.

Abstract: A current mirror circuit includes a first current mirror transistor, a second current mirror transistor, and a bias circuit. The first current mirror transistor includes a gate and a drain. The second current mirror transistor includes a gate coupled to the gate of the first current mirror transistor. The first current mirror transistor and the second current mirror transistor are low threshold voltage transistors. The bias circuit is coupled to the gate and the drain of the first current mirror transistor. The bias circuit is configured to bias the first current mirror transistor to operate in a saturation mode when a threshold voltage of the first current mirror transistor is a negative voltage.

Abstract: A system includes a power supply source and a power control circuit coupled to the power supply source, in which the power control circuit includes a pass field-effect transistor (FET). The system also includes a short-to-ground protection circuit coupled to an output of the pass FET. The short-to-ground protection circuit includes a sense circuit configured to detect when a magnitude and a change rate of a voltage drop at the output of the pass FET is greater than respective thresholds. The short-to-ground protection circuit also includes a control node at the output of the sense circuit. The sense circuit is configured to induce a control current at the control node in response to the magnitude and the change rate of a voltage drop at the output of the pass FET being greater than respective thresholds. The control current is used to turn off the pass FET.

Abstract: A system includes a power supply source and a power control circuit coupled to the power supply source, in which the power control circuit includes a pass field-effect transistor (FET). The system also includes a short-to-ground protection circuit coupled to an output of the pass FET. The short-to-ground protection circuit includes a sense circuit configured to detect when a magnitude and a change rate of a voltage drop at the output of the pass FET is greater than respective thresholds. The short-to-ground protection circuit also includes a control node at the output of the sense circuit. The sense circuit is configured to induce a control current at the control node in response to the magnitude and the change rate of a voltage drop at the output of the pass FET being greater than respective thresholds. The control current is used to turn off the pass FET.

Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

Abstract: A voltage regulator circuit includes a bias circuit having an input and an output. The input of the bias circuit is coupled to an input voltage supply rail. A Zener diode has a cathode coupled to the output of the bias circuit. A resistor network is coupled to the output of the bias circuit. The resistor network includes a first circuit path, which includes a first resistor, connected in parallel with the Zener diode and a second circuit path, which includes a second resistor, coupled between the output of the bias circuit and a node. A current control circuit is coupled to the bias circuit and the resistor network. An output stage has an input and an output. The input of the output stage is coupled to the node.

Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.

Abstract: Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

Abstract: In a described example, an apparatus includes at least one latch coupled to a first positive supply voltage and to a first negative supply voltage, the latch having a first inverter and a second inverter coupled to one another back to back, to output a first voltage corresponding to a first latch state and a second voltage corresponding to a second latch state responsive to a first set signal and a first reset signal. An isolation circuit is coupled to a second positive supply voltage and to a second negative supply voltage and is coupled to receive a second set signal, and a second reset signal. The second positive supply voltage is independent of the first positive supply voltage. The isolation circuit outputs the first set signal and the first reset signal and includes less than two pairs of drain extended metal oxide semiconductor (DEMOS) transistors.

Abstract: A voltage regulator (such as a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.

Abstract: A voltage regulator (e.g., a low drop-out regulator) includes a pass transistor coupled to an input voltage node and an output voltage node. The voltage regulator also includes a drive transistor coupled to a control input of the pass transistor and a first resistor coupled between a source and a back gate of the drive transistor. The voltage regulator also includes a complementary to absolute temperature (CTAT) current generator circuit coupled to the resistor and configured to generate a CTAT current to bias the first resistor.

Abstract: Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.