Abstract: An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: A data mover selection system includes a fabric manager system coupled to computing devices that are coupled to a memory system. The fabric manager system receives respective local data mover selection information from the computing devices that identifies data mover device(s) accessible to those computing device, and generates global data mover selection information that includes each data mover device accessible to the computing devices. When the fabric manager system receives a first data transfer request to transfer data between first and second memory locations in the memory system, it uses the global data mover selection information to identify a data mover device having the highest priority for performing data transfers between the first and second memory locations in the memory system, and transmits a first data transfer instruction to that data mover device to cause that data mover device to perform the first data transfer operation.

Abstract: A data mover selection system includes a memory system coupled to first and second data mover devices, and an operating system coupled to the first and second data mover devices. The operating system determines that a first data transfer operation provides for the transfer of data between first and second memory locations in the memory system, and identifies the first data mover device for performing the first data transfer operation based on the first data mover device having a higher priority relative to the second data mover device for performing data transfers between the first and second memory locations in the memory system. In response, the operating system transmits a first data transfer instruction to the first data mover device that causes the first data mover device to perform the first data transfer operation to transfer data between the first and second memory locations in the memory system.

Abstract: An I/O device selection system includes a memory system, I/O devices that are coupled to the memory system; and an I/O scheduler that is coupled to the I/O devices. The I/O scheduler receives an I/O request that that is directed to the memory system, and determines at least one I/O operation that is configured to satisfy the I/O request. The I/O scheduler then identifies an operating level of the I/O devices that are configured to perform the at least one I/O operation and, based on the operating level of the I/O devices, selects a subset of the I/O devices for performing the at least one I/O operation, and transmits at least one I/O operation instruction that is configured to cause the subset of the I/O devices to perform the at least one I/O operation in order to satisfy the I/O request.

Abstract: A data mover selection system includes a fabric manager system coupled to computing devices that are coupled to a memory system. The fabric manager system receives respective local data mover selection information from the computing devices that identifies data mover device(s) accessible to those computing device, and generates global data mover selection information that includes each data mover device accessible to the computing devices. When the fabric manager system receives a first data transfer request to transfer data between first and second memory locations in the memory system, it uses the global data mover selection information to identify a data mover device having the highest priority for performing data transfers between the first and second memory locations in the memory system, and transmits a first data transfer instruction to that data mover device to cause that data mover device to perform the first data transfer operation.

Abstract: An I/O device selection system includes a memory system, I/O devices that are coupled to the memory system; and an I/O scheduler that is coupled to the I/O devices. The I/O scheduler receives an I/O request that that is directed to the memory system, and determines at least one I/O operation that is configured to satisfy the I/O request. The I/O scheduler then identifies an operating level of the I/O devices that are configured to perform the at least one I/O operation and, based on the operating level of the I/O devices, selects a subset of the I/O devices for performing the at least one I/O operation, and transmits at least one I/O operation instruction that is configured to cause the subset of the I/O devices to perform the at least one I/O operation in order to satisfy the I/O request.

Abstract: A data mover selection system includes a memory system coupled to first and second data mover devices, and an operating system coupled to the first and second data mover devices. The operating system determines that a first data transfer operation provides for the transfer of data between first and second memory locations in the memory system, and identifies the first data mover device for performing the first data transfer operation based on the first data mover device having a higher priority relative to the second data mover device for performing data transfers between the first and second memory locations in the memory system. In response, the operating system transmits a first data transfer instruction to the first data mover device that causes the first data mover device to perform the first data transfer operation to transfer data between the first and second memory locations in the memory system.

Abstract: Software bus bridges (410.xy) are ordered in an order of associated bus identifiers (B), to allow programs accessing the corresponding physical bridges (310.xy) to find the correct software bus bridge either based on the bus identifiers, in which case the particular ordering of software bridges is unimportant, or based on the order of the software bridges. In some cases, this facilitates software porting across platforms with similar programmatic interfaces to the physical bridges but with different bus identifier ranges associated with physical bridges or with programmatic interfaces. A procedure is provided for determining the correct software bridge from a bus identifier. Other embodiments are also provided.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: A link downgrade detection system includes an interface that is coupled to an endpoint device. The endpoint device is configured to provide an endpoint link that includes a first link capability at a maximum first link capability level and a second link capability at a maximum second link capability level. The endpoint device stores a working first link capability level and a working second link capability level in a first memory device included on the endpoint device. A BIOS coupled to the chassis interface enumerates the endpoint device, determines an actual first link capability level and an actual second link capability level, and retrieves the working link capability levels. The BIOS then determines, based on the working link capability levels and the actual link capability levels that the endpoint link is downgraded, and in response provides a notification that the endpoint link of the endpoint device is downgraded.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: A processing system interconnect link training system includes a processing system that includes a secondary processing subsystem that is coupled to a first primary processing subsystem and a second primary processing system which are coupled to each other via a processing system interconnect that includes a plurality of processing system links. The secondary processing subsystem trains, during a boot operation and according to a first link configuration, the plurality of processing system links. Then the secondary processing subsystem determines that the training of the plurality of processing system links fails and, in response, retrains the plurality of processing system links according to a second link configuration that is a downgraded configuration relative to the first link configuration.

Abstract: In one or more embodiments, one or more systems, method, and/or processes may receive information from each of multiple components of an information handling system; may associate the information from each of the multiple components with at least one category of multiple categories; may store the information from each of the multiple components; may receive authorization information that includes a digital certificate that indicates authorization to the at least one category; may determine that the authorization information provides access to the at least one category; and in response to determining that the authorization information provides access to the at least one category: may provide the information from at least one component associated with the at least one category to a user; and may provide communications between the at least one component and the user.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: A processing system interconnect link training system includes a processing system that includes a secondary processing subsystem that is coupled to a first primary processing subsystem and a second primary processing system which are coupled to each other via a processing system interconnect that includes a plurality of processing system links. The secondary processing subsystem trains, during a boot operation and according to a first link configuration, the plurality of processing system links. Then the secondary processing subsystem determines that the training of the plurality of processing system links fails and, in response, retrains the plurality of processing system links according to a second link configuration that is a downgraded configuration relative to the first link configuration.

Abstract: An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Abstract: Software bus bridges (410.xy) are ordered in an order of associated bus identifiers (B), to allow programs accessing the corresponding physical bridges (310.xy) to find the correct software bus bridge either based on the bus identifiers, in which case the particular ordering of software bridges is unimportant, or based on the order of the software bridges. In some cases, this facilitates software porting across platforms with similar programmatic interfaces to the physical bridges but with different bus identifier ranges associated with physical bridges or with programmatic interfaces. A procedure is provided for determining the correct software bridge from a bus identifier. Other embodiments are also provided.

Abstract: A link downgrade detection system includes an interface that is coupled to an endpoint device. The endpoint device is configured to provide an endpoint link that includes a first link capability at a maximum first link capability level and a second link capability at a maximum second link capability level. The endpoint device stores a working first link capability level and a working second link capability level in a first memory device included on the endpoint device. A BIOS coupled to the chassis interface enumerates the endpoint device, determines an actual first link capability level and an actual second link capability level, and retrieves the working link capability levels. The BIOS then determines, based on the working link capability levels and the actual link capability levels that the endpoint link is downgraded, and in response provides a notification that the endpoint link of the endpoint device is downgraded.