Patents by Inventor Anh Khoa Lu

Anh Khoa Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two-dimensional material semiconductor device
    Patent number: 9899501
    Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: February 20, 2018
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Geoffrey Pourtois, Anh Khoa Lu, Cedric Huyghebaert
  • TWO-DIMENSIONAL MATERIAL SEMICONDUCTOR DEVICE
    Publication number: 20170179263
    Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 22, 2017
    Inventors: Geoffrey Pourtois, Anh Khoa Lu, Cedric Huyghebaert