Patents by Inventor Anhao CHENG

Anhao CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210020506
    Abstract: A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Anhao CHENG, Chun-Chang LIU
  • Patent number: 10811314
    Abstract: A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL).
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu
  • Publication number: 20200152589
    Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH
  • Publication number: 20200027964
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Application
    Filed: September 29, 2019
    Publication date: January 23, 2020
    Inventors: Anhao Cheng, Fang-Ting Kuo
  • Patent number: 10541218
    Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
  • Patent number: 10431664
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anhao Cheng, Fang-Ting Kuo
  • Publication number: 20190006488
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Application
    Filed: January 31, 2018
    Publication date: January 3, 2019
    Inventors: Anhao CHENG, Fang-Ting KUO
  • Publication number: 20180286784
    Abstract: A method of making a semiconductor device includes plating a first conductive material over a first passivation layer, wherein the first conductive material fills an opening in the first passivation layer and electrically connects to an interconnect structure. The method further includes planarizing the first conductive material, wherein a top surface of the planarized first conductive material is coplanar with a top surface of the first passivation layer. The method further includes depositing a second conductive material over the first passivation layer, wherein the second conductive material is different from the first conductive material, and the second conductive material is electrically connected to the first conductive material in the opening. The method further includes patterning the second conductive material to define a redistribution line (RDL).
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Anhao CHENG, Chun-Chang LIU
  • Patent number: 9991189
    Abstract: A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Anhao Cheng, Chun-Chang Liu
  • Publication number: 20180151525
    Abstract: A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.
    Type: Application
    Filed: January 6, 2017
    Publication date: May 31, 2018
    Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH
  • Publication number: 20180033745
    Abstract: A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Anhao CHENG, Chun-Chang LIU