Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

Abstract: A semiconductor structure includes a first isolation structure and a second isolation structure disposed in a substrate. The semiconductor structure includes a doped region interposed between the first isolation structure and the second isolation structure in the substrate. The semiconductor structure includes a gate structure disposed over the doped region. The semiconductor structure includes a first gate extension protruding from the gate structure into the first isolation structure, where the first gate extension has a first depth measured from a top surface of the substrate. The semiconductor structure further includes a second gate extension protruding from the gate structure into the second isolation structure, where the second gate extension has a second depth that is different from the first depth.

Abstract: A method is provided. The method includes determining a first hotspot region of a contact structure map. The method includes enlarging, according to a first predefined enlargement profile, the first hotspot region to determine a first enlarged region of the contact structure map. The method includes determining that a first portion of the first enlarged region overlaps a functional region of a functional component. The method includes determining a cropped region, of the contact structure map, that excludes the first portion of the first enlarged region. The method includes updating a first patterned oxide layer map based upon the cropped region to generate an updated patterned oxide layer map.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.

Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.

Abstract: A semiconductor device includes a first well region laterally separated from a second well region in a substrate, a shallow trench isolation (STI) structure laterally between the first well region and the second well region in the substrate, a first implant region of a dopant type opposite to a dopant type of the first well region in the substrate, disposed vertically lower than the STI structure and laterally between the first well region and a lateral center of the STI structure, and a second implant region of a dopant type opposite to a dopant type of the second well region in the substrate, disposed vertically lower than the STI structure and laterally between the second well region and the lateral center of the STI structure.

Abstract: A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.

Abstract: A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.

Abstract: A metal layer of a semiconductor device may be included in an extreme low dielectric constant (ELK) dielectric layer in an interconnect structure of the semiconductor device. The metal layer may be coupled with a bonding via that extends through a silicon carbide (SiC) layer in a bonding region of the semiconductor device. The ELK dielectric layer and/or the silicon carbide layer reduces stress migration in the semiconductor relative to the use of other dielectric materials such as silicon nitride and/or silicon glass. The ELK dielectric layer and/or the silicon carbide layer also reduces resistance-capacitance (RC) delay in the interconnect structure relative to the use of other dielectric materials. The ELK dielectric layer and/or the silicon carbide layer provides improved adhesion with the metal material(s) (e.g., copper and/or another metal material) of the metal layer and/or of the bonding via coupled with the metal layer.

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, where the first electrode bilayer includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the dielectric layer where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

Abstract: A semiconductor structure includes a substrate and a capacitor over the substrate. The capacitor includes a silicide layer over the substrate. The capacitor includes a first dielectric layer over the silicide layer. The capacitor includes a metal gate structure over the first dielectric layer, where a top portion of the metal gate structure is over the substrate and a bottom portion of the metal gate structure extends into the substrate. The capacitor includes a second dielectric layer over the metal gate structure. The capacitor further includes a conductive structure over the second dielectric layer.

Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

Abstract: A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Abstract: A semiconductor device includes a transistor, which includes a gate structure, a first source/drain structure, and a second source/drain structure. The gate structure is laterally disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and the second source/drain structure are formed in a first silicon layer disposed over a second silicon layer. The first silicon layer having at least a portion in direct contact with the second silicon layer. The second silicon layer includes a plurality of buried oxide layers.

Abstract: A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.

Abstract: An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.

Abstract: A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.

Abstract: In accordance with some aspects of the disclosure, a semiconductor structure is provided. The semiconductor structure includes: an active region; and a gate stack disposed on the active region. The gate stack includes: at least one gate dielectric layer disposed on the active region; and a metal gate structure disposed on the at least one gate dielectric layer. The metal gate structure includes: a metal gate layer comprising a first material; and at least one dummy structure disposed in the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material. The second material is different from the first material.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.