Patents by Inventor Anhao CHENG
Anhao CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978781Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.Type: GrantFiled: August 27, 2021Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Anhao Cheng, Fang-Ting Kuo, Yen-Yu Chen
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Patent number: 11955421Abstract: An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.Type: GrantFiled: August 30, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Anhao Cheng
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Publication number: 20240105751Abstract: A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.Type: ApplicationFiled: February 24, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Lei Chen, Anhao Cheng, Yen-Liang Lin
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Publication number: 20240071812Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, implanting n-type impurities into a device region in the semiconductor substrate to form an implanted region and an un-implanted region. The method also includes forming an epitaxial layer on the semiconductor substrate and forming a trench surrounding the device region in direct contact with the implanted region. The method further includes performing a selective lateral etch through the trench to remove the implanted region to form a cavity under the epitaxial layer. The un-implanted region is retained to form a pillar under the epitaxial layer. Next, an insulating material is disposed in the cavity and the trench. The method forms a single crystalline region that is separated from the semiconductor substrate by the insulating material except at the pillar.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
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Publication number: 20240021738Abstract: A semiconductor structure including a substrate, a first well region, a second well region, an isolation, a gate structure, and a dielectric layer is provided. The first well region is disposed in the substrate, wherein a dopant of the first well region includes arsenic. The second well region is disposed in the substrate under the first well region, wherein the second well region has a conductivity type different from that of the first doping region. The isolation is disposed in the substrate and surrounds the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate. The gate structure are disposed sequentially over the substrate and overlaps the first well region. A method of forming the semiconductor structure is also provided.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Inventors: ANHAO CHENG, CHING-HUNG KAO, YEN-LIANG LIN, MENG-I KANG, KAI-CHI WU, CHIEN-WEI LEE
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Publication number: 20230387244Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Anhao CHENG, Yen-Yu CHEN, Fang-Ting Kuo
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Publication number: 20230369450Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Anhao CHENG, Fang-Ting KUO
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Patent number: 11799014Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.Type: GrantFiled: January 14, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Anhao Cheng, Fang-Ting Kuo
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Publication number: 20230207313Abstract: A semiconductor device includes a first silicon layer. The semiconductor device includes a plurality of first buried oxide layers embedded in the first silicon layer. The semiconductor device includes a second silicon layer disposed over the plurality of first buried oxide layers. Vertical distances between the plurality of first buried oxide layers and the second silicon layer, respectively, are different.Type: ApplicationFiled: May 24, 2022Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Lei Chen, Anhao Cheng, Meng-I Kang, Yen-Liang Lin
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Publication number: 20230063995Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Inventors: Anhao CHENG, Fang-Ting KUO, Yen-Yu CHEN
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Publication number: 20230061546Abstract: An integrated circuit includes a plurality of transistors and an interlevel dielectric layer formed over the transistors. The interlevel dielectric layer includes a first region and a second region with a higher dielectric constant than the first region. The difference in dielectric constant is produced by curing the first region shielding the second region from the curing. Metal signal lines are formed in the first region. Metal-on-metal capacitors are formed in the second region.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventor: Anhao CHENG
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Publication number: 20220367606Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Anhao CHENG, Fang-Ting Kuo, Yen-Yu Chen
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Publication number: 20220352022Abstract: A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.Type: ApplicationFiled: July 14, 2022Publication date: November 3, 2022Inventors: Anhao CHENG, Chun-Chang LIU
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Publication number: 20220302060Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.Type: ApplicationFiled: June 2, 2022Publication date: September 22, 2022Inventors: Anhao CHENG, Chun-Chang LIU, Sheng-Wei YEH
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Patent number: 11410882Abstract: A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.Type: GrantFiled: October 5, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Anhao Cheng, Chun-Chang Liu
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Patent number: 11373970Abstract: A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes at least two post passivation interconnect (PPI) lines over the first passivation layer, wherein a top portion of each of the at least two PPI lines has a rounded shape. The semiconductor device further includes a second passivation layer configured to stress the at least two PPI lines. The semiconductor device further includes a polymer material over the second passivation layer and filling a trench between adjacent PPI lines of the at least two PPI lines.Type: GrantFiled: January 17, 2020Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Anhao Cheng, Chun-Chang Liu, Sheng-Wei Yeh
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Publication number: 20220140109Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Anhao CHENG, Fang-Ting KUO
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Patent number: 11227935Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.Type: GrantFiled: September 29, 2019Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Anhao Cheng, Fang-Ting Kuo
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Publication number: 20210305356Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Anhao CHENG, Fang-Ting KUO, Yen-Yu CHEN
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Publication number: 20210020506Abstract: A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: Anhao CHENG, Chun-Chang LIU