Abstract: In an aspect, a substrate for an integrated circuit (IC) package includes a first dielectric layer, a first metallization layer on a first surface of the first dielectric layer and including a first pad structure and a first trace structure, a second metallization layer on a second surface of the first dielectric layer and including a second pad structure and a second trace structure, a second dielectric layer on the second surface of the first dielectric layer, and a third metallization layer on a second surface of the second dielectric layer and having a third pad structure. The substrate further includes a conductive stud coupled to the second pad structure and a second via structure embedded in the second dielectric layer. The second via structure has a first end coupled to the conductive stud and a second end coupled to the third pad structure.

Abstract: A device includes a substrate that includes a first layer stack including multiple metal layers and multiple dielectric layers. A first metal layer includes contacts disposed in a first region and configured to electrically connect to a first IC device, via pads disposed in a second region, and traces electrically connected to the first contacts and to the via pads. One or more of the traces extend between a pair of the via pads. The substrate also includes a second layer stack disposed on the second region of the first metal layer. The second layer stack includes a dielectric layer and a second metal layer on the dielectric layer. The second metal layer defines second contacts configured to electrically connect to one or more second IC devices. The second layer stack also includes conductive vias extending between the via pads and the second contacts.

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the interposer structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the base structure. A width of the bond ball portion is greater than a width of the bond wire portion.

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the base structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the interposer structure. A width of the bond ball portion is greater than a width of the bond wire portion.

Abstract: Disclosed are package devices that include interconnects on first and second surfaces of a package substrate. The interconnects on the first surface of the package substrate are configured to carry general purpose input-output (GPIO) and miscellaneous IO signals. The interconnects on the second surface of the package substrate are configured to carry high speed input-output (HSIO) signals-signals whose speeds are above some minimum speed threshold. In this way, the package form can be reduced while still allowing for increased number of IO signals to be delivered.

Abstract: An integrated circuit (IC) device includes a substrate. The substrate includes a first side having a stepped configuration having a first surface that is elevated relative to a second surface. The first surface includes first solder resist openings (SROs), and the second surface includes second SROs. The IC device includes a first set of solder balls electrically connected to a first set of contacts in the first SROs. A solder ball of the first set of solder balls has a first characteristic dimension. The IC device also includes a second set of solder balls electrically connected to a second set of contacts in the second SROs. A solder ball of the second set of solder balls has a second characteristic dimension larger than the first characteristic dimension.

Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.

Abstract: A device includes a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer contacting the upper core dielectric layer and the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device includes an upper laminate stack coupled to the upper core dielectric layer. The upper laminate stack includes upper metal layers and contact pads configured to electrically connect a die to the passive electronic component by way of conductive paths defined by the set of upper metal layers. The device includes a lower laminate stack coupled to a bottom surface of the lower core dielectric layer. The lower laminate stack includes lower metal layers and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

Abstract: A substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. The core layer may include a glass material weaved throughout the core to provide stabilization and avoid warpage. A metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

Abstract: Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

Abstract: A device comprising a package. The package comprises a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of side wall interconnects coupled to the encapsulation layer and the metallization portion.

Abstract: In an aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises a bridge and/or an interposer, an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods. To provide for core layer of the substrate to support multiple embedded electrical devices, multiple core layers are provided in the substrate. Providing multiple core layers in the substrate allows multiple cavities to be formed in the core layers at multiple depths to compatibly support embedding of multiple electrical devices of varied thicknesses in the core layers. Thus, providing multiple core layers in the substrate can compatibly support forming cavities of multiple thicknesses that are compatible with multiple electrical devices of different thicknesses to be embedded therein. In this manner, design parameters of the overall thickness of the core layer of a substrate can be independent of the variation in thicknesses of multiple embedded electrical devices desired to be embedded therein.

Abstract: A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness. The package may include a substrate and/or a bridge. The substrate may include an interposer.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.