Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises a bridge and/or an interposer, an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods. To provide for core layer of the substrate to support multiple embedded electrical devices, multiple core layers are provided in the substrate. Providing multiple core layers in the substrate allows multiple cavities to be formed in the core layers at multiple depths to compatibly support embedding of multiple electrical devices of varied thicknesses in the core layers. Thus, providing multiple core layers in the substrate can compatibly support forming cavities of multiple thicknesses that are compatible with multiple electrical devices of different thicknesses to be embedded therein. In this manner, design parameters of the overall thickness of the core layer of a substrate can be independent of the variation in thicknesses of multiple embedded electrical devices desired to be embedded therein.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: A package comprising an integrated device and a metallization portion. The metallization portion comprises at least one dielectric layer and a plurality of metallization interconnects. The plurality of metallization interconnects comprise a first metallization interconnect located on a first metal layer and a second metallization interconnect located on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness that is different from the first thickness. The package may include a substrate and/or a bridge. The substrate may include an interposer.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

Abstract: Disclosed are apparatuses and techniques for fabricating the apparatuses. In an aspect, an apparatus includes an outer connection layer. The outer connection layer has an outer substrate and an outer metallization layer (ML). The outer ML includes a first set of sense split pads. The first set of sense split pads includes a first pad portion and a second pad portion and a test line. The test line is coupled to the first pad portion. The first pad portion and the second pad portion are electrically coupled to a same interconnect.

Abstract: A method is disclosed. The method includes receiving, by a server computer comprising a machine learning model, a fulfillment request including an address from an end user device operated by an end user. The method also includes determining an address type associated with the address, and performing, by the server computer, further processing based upon the address type.

Abstract: Disclosed is a stacked substrate package that incorporate surface mounted devices (SMD) between the base and interposer substrates. The SMDs, which may be passive devices (e.g., capacitor, inductor, resistor, etc.), may be electrically coupled to power distribution routing layers of the base and/or the interposer substrates. In this way, clean power may be provided to the devices (e.g., SoC dies, memory dies, etc.) of the stacked substrate package.

Abstract: Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

Abstract: A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Abstract: Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Abstract: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to the first surface of the substrate; wherein a back side of the second integrated device is coupled to a back side of the first integrated device through an adhesive. The substrate includes at least one dielectric layer and a plurality of interconnects. The substrate includes a flexible portion that is configured to be bend such that the back side of the first integrated device faces the back side of the second integrated device in the package.

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.

Abstract: A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

Abstract: A package comprising a first integrated device, a first metallization portion coupled to the first integrated device, a second integrated device, a second metallization portion coupled to the second integrated device and the first metallization portion, and an encapsulation layer coupled to the first metallization portion, the second integrated device and the second metallization portion. The first metallization portion includes at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion includes at least one second dielectric layer and a second plurality of metallization interconnects.

Abstract: Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

Abstract: An integrated power protection and conditioning system is disclosed. The integrated power protection and conditioning system includes a variable frequency drive (VFD) having a VFD housing and a power conversion circuit contained within the VFD housing and operable to provide a controlled output power to a load. The integrated power protection and conditioning system also includes a branch protection device having a branch protection housing and a power protection circuit contained within the outer housing and operable to selectively interrupt current flow from a power source to the VFD during a fault condition. The branch protection device is coupled to the VFD, such that the branch protection device is integrated with the VFD.