Patents by Inventor Anil Aggarwal

Anil Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070079301
    Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju Patel, Jason Brandt, Anil Aggarwal, John Reid
  • Patent number: 7194540
    Abstract: A mechanism is provided at a host system to allow multiple entities (clients) to send and receive messages of a particular class of management services in a switched fabric for scalable solutions.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: March 20, 2007
    Assignee: Intel Corporation
    Inventors: Anil Aggarwal, Oscar P. Pinto, Ashok Raj, Bruce M. Schlobohm, Rajesh R. Shah
  • Publication number: 20070006231
    Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Hong Wang, John Shen, Ed Grochowski, James Held, Bryant Bigbee, Shivnandan Kaushik, Gautham Chinya, Xiang Zou, Per Hammarlund, Xinmin Tian, Anil Aggarwal, Scott Rodgers, Prashant Sethi, Baiju Patel, Richard Hankins
  • Publication number: 20060294347
    Abstract: Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
    Type: Application
    Filed: May 19, 2005
    Publication date: December 28, 2006
    Inventors: Xiang Zou, Hong Wang, Scott Rodgers, Darrell Boggs, Bryant Bigbee, Shivanandan Kaushik, Anil Aggarwal, Ittai Anati, Doron Orenstein, Per Hammarlund, John Shen, Larry Smith, James Crossland, Chris Newburn
  • Publication number: 20060150183
    Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Inventors: Gautham Chinya, Hong Wang, Xiang Zou, James Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard Hankins, John Reid
  • Publication number: 20050219669
    Abstract: The present invention relates to a method of forming and validating a color-assigned rainbow security hologram of an object, where different parts of the recreated image of the object is presented to a viewer in different pre-chosen or assigned colors such that a novel in-built security verification/identification feature is encrypted/incorporated into these holograms, which can only be read/verified be using an encoded key hologram.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Applicant: COUNCIL OF SCIENTIFIC AND INDUSTRIAL
    Inventors: Sushil Kaura, Dharam Chhachhia, Anil Aggarwal, Ram Bajpai
  • Publication number: 20050027914
    Abstract: According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Per Hammalund, James Crossland, Shivnandan Kaushik, Anil Aggarwal
  • Publication number: 20040267996
    Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventors: Per Hammarlund, James B. Crossland, Anil Aggarwal, Shivnandan D. Kaushik
  • Publication number: 20030065775
    Abstract: A mechanism is provided at a host system to allow multiple entities (clients) to send and receive messages of a particular class of management services in a switched fabric for scalable solutions.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Anil Aggarwal, Oscar P. Pinto, Ashok Raj, Bruce M. Schlobohm, Rajesh R. Shah