Abstract: In one example implementation according to aspects of the present disclosure, a system is provided that includes a host processing system and a memory device communicatively coupled to the host processing system. The memory device includes a memory device controller, a volatile memory module, and a non-volatile memory module. The memory device controller performs a method including writing a data pattern to the non-volatile memory module, reading the data pattern from the non-volatile memory module, comparing the data pattern from the non-volatile memory module to an expected data pattern, and, based at least in part on determining that the data pattern from the non-volatile memory module matches the expected data pattern, loading system data stored in the volatile memory module to the non-volatile memory module when the host processing system experiences a power loss.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Abstract: The present invention provides a computer implemented method, system, and computer program product of assessing in-field reliability of computer memories. In an embodiment, the present invention includes taking control of a portion of a computer memory circuit, utilizing a portion of a computer memory bus associated with the portion of the computer memory circuit, moving computer memory circuit data stored in the portion of the computer memory circuit to a host computer storage device, executing a set of logical operations assessing reliability of the portion of the computer memory circuit, resulting in assessment data stored in a reliability error monitor (REM) computer storage device, transmitting the stored assessment data from the REM computer storage device to a computer memory controller circuit, and in response to the transmitting, moving the moved computer memory circuit data from the host computer storage device back to the portion of the computer memory circuit.

Abstract: The present invention provides a computer implemented method, system, and computer program product of assessing in-field reliability of computer memories. In an embodiment, the present invention includes taking control of a portion of a computer memory circuit, utilizing a portion of a computer memory bus associated with the portion of the computer memory circuit, moving computer memory circuit data stored in the portion of the computer memory circuit to a host computer storage device, executing a set of logical operations assessing reliability of the portion of the computer memory circuit, resulting in assessment data stored in a reliability error monitor (REM) computer storage device, transmitting the stored assessment data from the REM computer storage device to a computer memory controller circuit, and in response to the transmitting, moving the moved computer memory circuit data from the host computer storage device back to the portion of the computer memory circuit.

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.

Abstract: A system and method are provided for sharing capacitance. The system may include a first electronic entity with a capacitor having capacitance. The system may further include a switched path in the first electronic entity. The switched path may have a first switched position in which the switched path provides the capacitance to a voltage using device in first electronic entity. The switched path may also have a second switched position in which the switched path provides the capacitance to a second electronic entity. The switched path may also have a third switched position in which the switched path provides the capacitance to both the voltage-using device in the first electronic entity and the second electronic entity.

Abstract: A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.

Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.