Abstract: Methods and apparatus for pillar bending improvement by cut tiers pattern implementation. The method uses a cut tier pattern in a staircase region of a 3D memory structure to reduce pillar bending in a pillar array region. The pillar array region includes a plurality of memory tiers comprising wordline layers interposed between isolation layers, where a memory tier comprises a two-dimensional (2D) array of memory cells. A plurality of vertical structures comprising pillars pass through memory cells in the wordline layers and pass through the isolation layers. The staircase structure is disposed adjacent to the pillar array region and includes vertical wordline drivers coupled to the wordline layers. A cut tier pattern comprising vertical trenches is formed in the staircase structure toward a side of the staircase structure adjacent to the pillar array region. The cut tier pattern includes one or more breaks used for routing circuitry in the wordlines.

Abstract: An apparatus is described. The apparatus includes a flash memory chip having a self-aligned dielectric fill between pillars. The self-aligned dielectric fill extends through a polysilicon layer. The pillars have respective access transistors formed with the polysilicon layer. The self-aligned dielectric fill to electrically isolate the pillars.

Abstract: A semiconductor circuit includes multiple decks of semiconductor devices, each deck having multiple three-dimensional (3D) stacks. The semiconductor circuit has a nitride layer between the first deck and the second deck. The nitride layer has a self-aligned pillar through the nitride layer to electrically connect the first deck to the second deck. The nitride layer can have multiple sublayers, with a mirrored gradient doping, with lower doping toward the middle of the nitride layer and higher doping toward the outsides of the nitride layer that interfaces with the decks.