Patents by Inventor Anil K. Patel

Anil K. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922220
    Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
  • Patent number: 5913923
    Abstract: A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: June 22, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Frederick S. Dunlap, Anil K. Patel