Abstract: The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Abstract: In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

Abstract: In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.

Abstract: A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.

Abstract: A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

Abstract: A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

Abstract: A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.

Abstract: According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.

Abstract: According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.