Patents by Inventor Anil Kumar BARATAM
Anil Kumar BARATAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900039Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.Type: GrantFiled: February 13, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Anil Kumar Baratam, Jr., Subramanya Ravindra Shindagikar
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Publication number: 20230063727Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Anil Kumar Baratam, Yves Thomas Laplanche
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Patent number: 11586445Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: GrantFiled: November 27, 2019Date of Patent: February 21, 2023Assignee: Arm LimitedInventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Patent number: 11456727Abstract: Various implementations described herein are directed to a device having multiple stages. The device may have a first stage that provides a data path for an input data signal. The first stage may receive the input data signal, receive feedback signals, and provide an intermediate data signal based on the input data signal and/or the feedback signals. The device may have a second stage that provides set/reset signals based on the intermediate data signal and/or a clock signal. The second stage may receive the intermediate data signal, receive the clock signal, and generate the set/reset signals based on the intermediate data signal and the clock signal. The second stage may also provide the set/reset signals as the feedback signals to the first stage.Type: GrantFiled: October 20, 2020Date of Patent: September 27, 2022Assignee: Arm LimitedInventor: Anil Kumar Baratam
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Patent number: 11405040Abstract: Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.Type: GrantFiled: August 12, 2020Date of Patent: August 2, 2022Assignee: Arm LimitedInventor: Anil Kumar Baratam
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Publication number: 20220123737Abstract: Various implementations described herein are directed to a device having multiple stages. The device may have a first stage that provides a data path for an input data signal. The first stage may receive the input data signal, receive feedback signals, and provide an intermediate data signal based on the input data signal and/or the feedback signals. The device may have a second stage that provides set/reset signals based on the intermediate data signal and/or a clock signal. The second stage may receive the intermediate data signal, receive the clock signal, and generate the set/reset signals based on the intermediate data signal and the clock signal. The second stage may also provide the set/reset signals as the feedback signals to the first stage.Type: ApplicationFiled: October 20, 2020Publication date: April 21, 2022Inventor: Anil Kumar Baratam
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Patent number: 11245388Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.Type: GrantFiled: January 10, 2020Date of Patent: February 8, 2022Assignee: Arm LimitedInventors: Navaneeth Narayanan Namboodiri Rajalakshmi, Anil Kumar Baratam
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Publication number: 20210305985Abstract: Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.Type: ApplicationFiled: August 12, 2020Publication date: September 30, 2021Inventor: Anil Kumar Baratam
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Publication number: 20210218389Abstract: Various implementations described herein may refer to level shifter circuitry using current mirrors. For instance, in one implementation, a level shifter circuit may include a latch circuit configured to receive an input signal, where the latch circuit includes a plurality of transistors configured to generate an output signal based on the input signal. The level shifter circuit may also include a first current mirror circuit coupled to the latch circuit. The level shifter circuit may further include a second current mirror circuit coupled to the latch circuit, where the first current mirror circuit and the second current mirror circuit are configured to drive the output signal from a transient state voltage level to a steady state voltage level.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: Navaneeth Narayanan Namboodiri Rajalakshmi, Anil Kumar Baratam
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Publication number: 20210165945Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.Type: ApplicationFiled: February 13, 2021Publication date: June 3, 2021Inventors: Anil Kumar Baratam, JR., Subramanya Ravindra Shindagikar
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Publication number: 20210157603Abstract: Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Shardendu Shekhar, Andy Wangkun Chen, Anil Kumar Baratam, James Dennis Dodrill, Yew Keong Chong
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Patent number: 10922465Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.Type: GrantFiled: September 27, 2018Date of Patent: February 16, 2021Assignee: Arm LimitedInventors: Anil Kumar Baratam, Subramanya Ravindra Shindagikar
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Publication number: 20200104444Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Inventors: Anil Kumar Baratam, Subramanya Ravindra Shindagikar
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Patent number: 10355674Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.Type: GrantFiled: July 24, 2017Date of Patent: July 16, 2019Assignee: ARM LimitedInventors: Anil Kumar Baratam, Nruthya Nagesh Prabhu, Yves Thomas Laplanche
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Publication number: 20190028091Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.Type: ApplicationFiled: July 24, 2017Publication date: January 24, 2019Inventors: Anil Kumar Baratam, Nruthya Nagesh Prabhu, Yves Thomas Laplanche
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Patent number: 10187063Abstract: Various implementations described herein are directed to a sequential logic device having multiple stages. The sequential logic device may include a first stage having first transistors that are arranged to receive a data input signal and a clock signal and provide a first signal and a second signal based on the data input signal and the clock signal. The sequential logic device may include a second stage having second transistors that are arranged to receive the first signal from the first stage and provide an inverted first signal to a gate of a first pass transistor. The first pass transistor may allow the second signal to pass from the first stage to a second pass transistor based on the inverted first signal, and the second pass transistor may allow the second signal to pass from the first pass transistor to ground based on the clock signal.Type: GrantFiled: November 29, 2017Date of Patent: January 22, 2019Assignee: ARM LimitedInventors: Amanda Ashley Scantlin, Anil Kumar Baratam, James Dennis Dodrill, Susan Marie Graham
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Patent number: 9306545Abstract: A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop.Type: GrantFiled: January 14, 2014Date of Patent: April 5, 2016Assignee: ARM LimitedInventor: Anil Kumar Baratam
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Publication number: 20150200651Abstract: A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop.Type: ApplicationFiled: January 14, 2014Publication date: July 16, 2015Applicant: ARM LIMITEDInventor: Anil Kumar BARATAM