Abstract: The multiplier circuit has as input signals an M bit multiplicand and an N bit multiplier and outputs a M+N bit product. The multiplier circuit includes a number of recoder circuits. The recoder circuits recode the N bit multiplier into fewer bits, thereby reducing the longest signal path through the multiplier circuit and increasing the speed of the circuit. In one embodiment, the recoder circuits perform a N to N/2 Booth recoding. The recoder circuits are combined with other circuitry to generate partial products. The partial products are combined in a three to two compression circuit. The compression circuit further reduces the longest signal path through the multiplier circuit. In one embodiment, the three to two compression circuits are configured in a Wallace Tree. In another embodiment, four to two compression circuits are used. The compression circuit outputs two addends. The two addends are then added in an adder to generate the product.