Patents by Inventor Anil Sharma

Anil Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12327581
    Abstract: Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 10, 2025
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Abhishek Anil Sharma, Uygar Avci
  • Patent number: 12236280
    Abstract: An orchestration layer for execution user defined automation workflows. The orchestration layer may include multiple process instances that host user defined automation workflows that automate processes or tasks. To improve system performance and reduce operating costs, the user defined automation workflows are deployed to the orchestration layer in a standard format that standardizes the user defined workflow configurations. The orchestration layer may also dynamically scale the computational resources allocated to teach process instance based on the properties of each user defined automation workflow.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 25, 2025
    Assignee: Intuit Inc.
    Inventors: Siben Nayak, Govinda Sambamurthy, Nishant Sehgal, Anil Sharma, Srivatsan Vijayaraghavan, Suraj Menon, Shyamalendu Tripathy, Jatin Mahajan, Nivedita Nayak, Sachin Gupta
  • Patent number: 12211794
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 28, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Anil Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Publication number: 20250006812
    Abstract: N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Applicant: INTEL CORPORATION
    Inventors: Sudipto Naskar, Sukru Yemenicioglu, Abhishek Anil Sharma, Van Le, Weimin Han
  • Publication number: 20240429901
    Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Steven K. Hsu, Amit Agarwal, Abhishek Anil Sharma, Ram K. Krishnamurthy
  • Patent number: 12174875
    Abstract: Computer-implemented processes and systems described herein are directed to reducing volumes of data sent from edge devices to a data center. Each edge device runs an agent that collects event information generated by event sources of the edge device in a runtime interval. Each agent reduces the event information to relevant event information at the edge device in accordance with instructions received from a controller server of the data center. The relevant event information contains less information than the event information. Each agent forwards the relevant event information over the internet to external services executed at the data center, where the relevant event information is stored in a data storage device of the data center.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 24, 2024
    Assignee: VMware LLC
    Inventors: Anil Sharma, Darren Brown, Pedro Algarvio, Caleb Beard
  • Publication number: 20240332285
    Abstract: An integrated circuit device comprising a resistor formed on a non-crystalline substrate, the resistor comprising a gate electrode; a gate dielectric in contact with the gate electrode; a source electrode and a drain electrode; and a thin film transistor TFT channel material coupled between the source electrode and the drain electrode.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Sukru Yemenicioglu, Abhishek Anil Sharma, Sudipto Naskar, Kalyan C. Kolluru, Chu-Hsin Liang, Bashir Uddin Mahmud, Van Le
  • Publication number: 20240332432
    Abstract: An integrated circuit device comprising a varactor comprising a first conductive contact; a second conductive contact; and a thin film transistor (TFT) channel material coupled between the first conductive contact and the second conductive contact.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Sukru Yemenicioglu, Abhishek Anil Sharma, Sudipto Naskar, Kalyan C. Kolluru
  • Publication number: 20240332299
    Abstract: An integrated circuit device comprising a plurality of first field effect transistors (FETs) formed on a substrate, wherein a first FET comprises a first channel material comprising a portion of the substrate; and a plurality of second FETs formed on the substrate, wherein a second FET comprises a second channel material that is different from the first channel material, wherein the second channel material comprises a thin film transistor (TFT) channel material.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Van Le, Sudipto Naskar, Sukru Yemenicioglu
  • Publication number: 20240324167
    Abstract: A high performance (HP) thin film transistor (TFT) architecture to enable fabricating backside memory after metallization starts, or as part of back end of line (BEOL) processes. The HP TFT material is suitable for fabricating the memory stack at the lower BEOL temperatures while still delivering the switching speed requirements of a 3D memory stack in the CIM component. A through silicon via (TSV) architecture connects the logic and the memory in the die.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Sudipto Naskar, Abhishek Anil Sharma, Sukru Yemenicioglu, Weimin Han, Van Le
  • Patent number: 12067376
    Abstract: A workflow construction system for constructing automation workflows that automate user specific processes. The workflow construction system may include a template library including workflow templates and pre-configured attributes. The workflow template can accelerate the design and construction of custom automation workflows. An orchestration layer included in the workflow construction system will also improve the performance of systems that execute the automation workflows by dynamically scaling the processing capacity, memory, and storage of servers and other systems hosting the model file instances of the automation workflows to ensure the available resources meet the demands of users completing processes using the automation workflows.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: August 20, 2024
    Inventors: Siben Nayak, Govinda Sambamurthy, Anil Sharma, Srivatsan Vijayaraghavan, Nishant Sehgal, Sandeep Gupta, Shirish Peshwe, Archit Singh, Harsh Madhogaria, Jitin Maherchandani, Shyamalendu Tripathy
  • Publication number: 20240224504
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that include DRAM using wide band gap materials, such as SiC or GaN to reduce transistor leakage. In addition, transistors may be fabricated adding one or more extra layers between a source and a drain of a transistor and the contact of the source of the drain to increase the effective electrical gate length of the transistor to further reduce leakage. In addition, for these transistors, a thickness of the body below the gate may be made narrow to improve gate control. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Han Wui THEN, Pushkar RANADE, Wilfred GOMES, Sagar SUTHRAM, Tahir GHANI, Anand S. MURTHY
  • Publication number: 20240222272
    Abstract: Stitched dies having double interconnects are described. For example, an integrated circuit structure includes a first die including a first device layer, a first plurality of metallization layers over the first device layer, and a first conductive interconnection over the first plurality of metallization layers. The integrated circuit structure also includes a second die separated from the first die by a scribe region, the second die including a second device layer, a second plurality of metallization layers over the second device layer, and a second conductive interconnection over the second plurality of metallization layers. The second conductive interconnection extends over the scribe region and is coupled to the first conductive interconnection.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Christopher M. PELTO, Wilfred GOMES, Tahir GHANI, Anand S. MURTHY
  • Publication number: 20240222469
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use high voltage transistors within a SiC layer that are coupled with one or more transistors in one or more other layers in a cascode format in order to switch the high voltage transistors in the SiC layer using low voltages. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Han Wui THEN, Wilfred GOMES, Tahir GHANI, Anand S. MURTHY, Sagar SUTHRAM, Pushkar RANADE
  • Publication number: 20240222347
    Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Kuljit S. Bains, Wilfred Gomes, Don Douglas Josephson, Surhud V. Khare, Christopher Philip Mozak, Randy B. Osborne, Pushkar Ranade, Abhishek Anil Sharma
  • Publication number: 20240222438
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for designing and fabricating semiconductor packages that include transistors that include wide band gap materials, such as silicon carbide or gallium nitride. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Han Wui THEN, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES, Sagar SUTHRAM, Pushkar RANADE
  • Publication number: 20240224536
    Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Jack T. KAVALIEROS, Anand S. MURTHY, Wilfred GOMES
  • Publication number: 20240222276
    Abstract: Structures having lookup table decoders for FPGAs with high DRAM transistor density are described. In an example, an integrated circuit structure includes a plurality of fins or nanowire stacks, individual ones of the plurality of fins or nanowire stacks having a longest dimension along a first direction. A plurality of gate structures is over the plurality of fins or nanowire stacks, individual ones of the plurality of gate structures having a longest dimension along a second direction, wherein the first direction is non-orthogonal to the second direction.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Sagar SUTHRAM, Pushkar RANADE, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES
  • Publication number: 20240224508
    Abstract: Structures having bit-cost scaling with relaxed transistor area are described. In an example, an integrated circuit structure includes a plurality of plate lines along a first direction. A transistor is beneath the plurality of plate lines, with a direction of a first source or drain to a gate to a second source or drain of the transistor being a second direction orthogonal to the first direction. A plurality of capacitor structures is over the plurality of plate lines, individual ones of the plurality of capacitor structures coupled to a corresponding one of the plurality of plate lines. The plurality of capacitor structures has a staggered arrangement from a plan view perspective.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES, Pushkar RANADE, Sagar SUTHRAM
  • Publication number: 20240222435
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for fabricating semiconductor packages that use a SiC layer that is coupled with another layer that includes another material. The SiC layer may be an active layer that includes devices, such as transistors, that are coupled with devices that may be in the other layer. The SiC layer may be coupled with the other layer using fusion bonding, hybrid bonding, layer transfer, and/or bump and island formation techniques. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Abhishek Anil SHARMA, Han Wui THEN, Wilfred GOMES, Anand S. MURTHY, Tahir GHANI, Sagar SUTHRAM, Pushkar RANADE