Abstract: A system and method for controlling data access in a memory system is disclosed. The memory system is characterized by the use of a transport and retire write request, memory devices incorporating a retire buffer, and inherent data retirement. Addresses associated with un-retired write data are stored in the memory controller and compared to the address of a read request following one or more write requests. Where a read request is directed to an address associated with an un-retired write data, the read request is stalled in the memory controller.

Abstract: A system and method for controlling data access in a memory system is disclosed. The memory system is characterized by the use of a transport and retire write request, memory devices incorporating a retire buffer, and inherent data retirement. Addresses associated with un-retired write data are stored in the memory controller and compared to the address of a read request following one or more write requests. Where a read request is directed to an address associated with an un-retired write data, the read request is stalled in the memory controller.

Abstract: A high-speed bus subsystem includes a plurality of bus channels, wherein each bus channel has an independent channel clock signal generated by an associated channel clock generator. A master device or other interface component receives and utilizes a system clock signal and a channel clock signal for each channel. For each channel, a derivative of the system clock signal and a derivative of the channel clock signal are routed to a clock generator. The clock generator compares the received signals, and generates its channel clock signal at a phase which eliminates any significant phase difference between the system clock signal and the channel clock signal.

Abstract: A memory controller includes a constraint tracking and checking unit for tracking and checking timing constraints imposed by respective issued commands to access a memory. A constraint tracking subunit includes multiple tracking circuits and an allocation circuit. The allocation circuit is configured to allocate a selected tracking circuit from among the multiple tracking circuits each time that a specific command is issued. The allocated tracking circuit is configured to track the timing constraint imposed by the specific command. A constraint checking subunit is configured to determine if the tracked timing constraint is pending against issuance of a generated command to access the memory and to generate a blocking signal when a timing constraint is pending against issuance of a generated command.