Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.

Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

Abstract: Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

Abstract: Aspects of the invention provide for reducing power consumption during manufacturing testing of an IC. In one embodiment, aspects of the invention include a method for reducing power consumption during a manufacturing test of an integrated circuit (IC), the method including: providing a plurality of domains, each domain associated with a clock phase; grouping, based on each domain, a first plurality of scan chains into a first test group; grouping, based on each domain, a second plurality of scan chains into a second test group, wherein the grouping of the first test group and of the second test group includes determining which domains can be tested simultaneously; and performing the manufacturing test of the IC.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.

Abstract: A method and system for testing a synthesized design of a semiconductor chip. The method includes inputting a macro test Input/Output (I/O) name of the semiconductor chip, along with associated attributes and a netlist, where the netlist is a synthesized design of the semiconductor chip. The method includes tracking the macro test I/O to a chip test I/O. The method further includes detecting mismatches between attributes associated with the macro test I/O and the chip test I/O. Subsequently, reporting any mismatches between the attributes associated with the macro test I/O and the chip test I/O.