Patents by Inventor Animesh PAUL
Animesh PAUL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250038751Abstract: In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.Type: ApplicationFiled: October 14, 2024Publication date: January 30, 2025Inventor: Animesh PAUL
-
Publication number: 20240388253Abstract: An oscillator apparatus, including a first node adapted to be coupled to a first terminal of a crystal oscillator; a second node adapted to be coupled to a second terminal of the crystal oscillator; a transconductance circuit; a first switch coupled between the first node and the second node; and a second switch coupled between the transconductance circuit and the second node.Type: ApplicationFiled: July 25, 2024Publication date: November 21, 2024Inventor: ANIMESH PAUL
-
Patent number: 12136926Abstract: In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.Type: GrantFiled: November 22, 2022Date of Patent: November 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Animesh Paul
-
Patent number: 12074569Abstract: An oscillator apparatus, including a first node adapted to be coupled to a first terminal of a crystal oscillator; a second node adapted to be coupled to a second terminal of the crystal oscillator; a transconductance circuit; a first switch coupled between the first node and the second node; and a second switch coupled between the transconductance circuit and the second node.Type: GrantFiled: November 30, 2022Date of Patent: August 27, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Animesh Paul
-
Publication number: 20240178794Abstract: An oscillator apparatus, including a first node adapted to be coupled to a first terminal of a crystal oscillator; a second node adapted to be coupled to a second terminal of the crystal oscillator; a transconductance circuit; a first switch coupled between the first node and the second node; and a second switch coupled between the transconductance circuit and the second node.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Inventor: ANIMESH PAUL
-
Publication number: 20240136975Abstract: An integrated circuit, with an error amplifier having a first input, a second input, and an output, a voltage controlled oscillator having an input coupled to the output of the error amplifier, a feedback controlled voltage stage having at least one control coupled to the output of the error amplifier and an output coupled to the first input of the error amplifier, and an adaptive-reference voltage stage coupled to the second input of the error amplifier.Type: ApplicationFiled: November 30, 2022Publication date: April 25, 2024Inventor: ANIMESH PAUL
-
Publication number: 20240137028Abstract: In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.Type: ApplicationFiled: November 22, 2022Publication date: April 25, 2024Inventor: Animesh PAUL
-
Patent number: 10615780Abstract: In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.Type: GrantFiled: December 8, 2017Date of Patent: April 7, 2020Assignee: QUALCOMM IncorporatedInventors: Animesh Paul, Xinhua Chen
-
Publication number: 20190181844Abstract: In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.Type: ApplicationFiled: December 8, 2017Publication date: June 13, 2019Inventors: Animesh Paul, Xinhua Chen
-
Publication number: 20190181843Abstract: Dividers based on quadrature ring oscillators using conventional latch devices can suffer from high current consumption. This is because there can be a number of short-circuit current paths during the output transitions of the conventional latch devices. To address this issue, a latch device with a novel locking cell is proposed. Unlike the conventional latch device, the transistors of the proposed locking cell may all be of a same transistor type. The configuration of the proposed locking cell eliminates a number of the short-circuit currents compared to the conventional latch device. As a result, power consumption can be reduced.Type: ApplicationFiled: December 13, 2017Publication date: June 13, 2019Inventors: Animesh PAUL, Xinhua CHEN, Shailesh RAI
-
Patent number: 9998129Abstract: A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.Type: GrantFiled: September 21, 2017Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Jingcheng Zhuang, Jianyun Hu, Animesh Paul, Xinhua Chen, Frederic Bossu
-
Patent number: 9973182Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: GrantFiled: September 14, 2016Date of Patent: May 15, 2018Assignee: QUALCOMM IncorporatedInventors: Animesh Paul, Jingcheng Zhuang, Xinhua Chen, Ravi Sridhara
-
Publication number: 20180102772Abstract: Certain aspects of the present disclosure generally relate to generating clock signals. For example, certain aspects of the present disclosure provide a multi-stage clock generation circuit. The multi-stage clock generation circuit generally includes a first clock-generation stage comprising first cascode-connected transistors the first cascode-connected transistors having gates coupled to a first input clock node. The multi-stage clock generation circuit may also include a second clock-generation stage comprising second cascode-connected transistors, the second cascode-connected transistors having gates coupled to a second input clock node. A first transistor may be coupled to the second cascode-connected transistors, the first transistor having a gate coupled to drains of the first cascode-connected transistors.Type: ApplicationFiled: October 11, 2016Publication date: April 12, 2018Inventors: Animesh PAUL, Xinhua CHEN
-
Publication number: 20180076805Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.Type: ApplicationFiled: September 14, 2016Publication date: March 15, 2018Inventors: Animesh PAUL, Jingcheng ZHUANG, Xinhua CHEN, Ravi SRIDHARA