Patents by Inventor Animesh Sharma

Animesh Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230224256
    Abstract: Examples described herein relate to method, resource management system, and non-transitory machine-readable medium for redeploying a computing resource. Data related to a performance parameter corresponding to a plurality of computing resources deployed on a plurality of host-computing nodes may be received. The performance parameter is associated with one or both of: communication between computing resources of the plurality of computing resources, or communication of the plurality of computing resources with a network device. Further, for a computing resource of the plurality of computing resources, a candidate host-computing node is determined from the plurality of host-computing nodes based on the data related to the performance parameter and the computing resource may be redeployed on the candidate host-computing node.
    Type: Application
    Filed: February 27, 2023
    Publication date: July 13, 2023
    Inventors: Siddhartha Singh, Animesh Sharma
  • Patent number: 11616732
    Abstract: Examples described herein relate to method, resource management system, and non-transitory machine-readable medium for redeploying a computing resource. Data related to a performance parameter corresponding to a plurality of computing resources deployed on a plurality of host-computing nodes may be received. The performance parameter is associated with one or both of: communication between computing resources of the plurality of computing resources, or communication of the plurality of computing resources with a network device. Further, for a computing resource of the plurality of computing resources, a candidate host-computing node is determined from the plurality of host-computing nodes based on the data related to the performance parameter and the computing resource may be redeployed on the candidate host-computing node.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 28, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Siddhartha Singh, Animesh Sharma
  • Patent number: 11193964
    Abstract: A method of determining stress within a composite structure is provided which includes coupling a sensor to a composite structure under load having embedded therein a plurality of particles, wherein the particles at room temperature are paraelectric or ferroelectric, transmitting an electromagnetic radiation to the sensor, thereby generating an electromagnetic field into the composite structure, sweeping frequency from a first frequency to a second frequency in a pulsed manner, receiving reflected power from the composite structure, determining the resonance frequency of the sensor, and translating the resonance frequency of the sensor to stress within the composite structure.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 7, 2021
    Assignee: Purdue Research Foundation
    Inventors: Abhijeet Dhiman, Vikas Tomar, Animesh Sharma, Alexey Shashurin, Sergey O Macheret
  • Publication number: 20210377184
    Abstract: Examples described herein relate to method, resource management system, and non-transitory machine-readable medium for redeploying a computing resource. Data related to a performance parameter corresponding to a plurality of computing resources deployed on a plurality of host-computing nodes may be received. The performance parameter is associated with one or both of: communication between computing resources of the plurality of computing resources, or communication of the plurality of computing resources with a network device. Further, for a computing resource of the plurality of computing resources, a candidate host-computing node is determined from the plurality of host-computing nodes based on the data related to the performance parameter and the computing resource may be redeployed on the candidate host-computing node.
    Type: Application
    Filed: April 20, 2021
    Publication date: December 2, 2021
    Inventors: Siddhartha Singh, Animesh Sharma
  • Publication number: 20190369149
    Abstract: A method of determining stress within a composite structure is provided which includes coupling a sensor to a composite structure under load having embedded therein a plurality of particles, wherein the particles at room temperature are paraelectric or ferroelectric, transmitting an electromagnetic radiation to the sensor, thereby generating an electromagnetic field into the composite structure, sweeping frequency from a first frequency to a second frequency in a pulsed manner, receiving reflected power from the composite structure, determining the resonance frequency of the sensor, and translating the resonance frequency of the sensor to stress within the composite structure.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 5, 2019
    Applicant: Purdue Research Foundation
    Inventors: ABHIJEET DHIMAN, Vikas Tomar, Animesh Sharma, Alexey Shashurin, Sergey O Macheret
  • Patent number: 9625938
    Abstract: A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal. The apparatus includes a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: April 18, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hariprasad Thodukattil Thazhatheppattu, Prasant Vallur, Animesh Sharma
  • Publication number: 20160285437
    Abstract: A technique implements differential digital logic circuits with a differential clock distribution network using standard cell differential clock gater circuits to reduce area, delay, power consumption in integrated circuits. An apparatus includes a first terminal configured to receive a clock signal, a second terminal configured to receive a complementary clock signal, and a third terminal configured to receive a clock control signal. The apparatus includes a latch circuit configured to generate a latched version of the clock control signal based on a version of the clock control signal, a version of the clock signal, and a version of the complementary clock signal. The apparatus includes a combinatorial circuit configured to generate a gated clock signal and a gated complementary clock signal based on the version of the clock control signal, the version of the clock signal, and the version of the complementary clock signal.
    Type: Application
    Filed: March 25, 2015
    Publication date: September 29, 2016
    Inventors: Hariprasad Thodukattil Thazhatheppattu, Prasant Vallur, Animesh Sharma