Patents by Inventor Anindya Nath
Anindya Nath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12376385Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.Type: GrantFiled: June 7, 2022Date of Patent: July 29, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Anindya Nath, Rajendran Krishnasamy, Robert J. Gauthier, Jr.
-
Publication number: 20250221055Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; and a triggering device adjacent to the vertical silicon controlled rectifier, the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.Type: ApplicationFiled: January 3, 2024Publication date: July 3, 2025Inventors: Sagar Premnath KARALKAR, Alain F. LOISEAU, Meng MIAO, Anindya NATH, Wei LIANG, Souvick MITRA, Rajendran KRISHNASAMY
-
Patent number: 12324248Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge device (ESD) with a pinch resistor and methods of manufacture. The structure includes: a semiconductor substrate; a shallow trench isolation structure extending into the semiconductor substrate; an amorphous layer in the semiconductor substrate and below the shallow trench isolation structure; and a pinch resistor between the shallow trench isolation structure and the amorphous layer.Type: GrantFiled: June 16, 2022Date of Patent: June 3, 2025Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Anindya Nath, Robert J. Gauthier, Jr., Rajendran Krishnasamy
-
Patent number: 12293994Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.Type: GrantFiled: September 28, 2022Date of Patent: May 6, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Vvss Satyasuresh Choppalli, Anupam Dutta, Rajendran Krishnasamy, Robert Gauthier, Jr., Xiang Xiang Lu, Anindya Nath
-
Publication number: 20250126817Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.Type: ApplicationFiled: October 17, 2023Publication date: April 17, 2025Inventors: Meng Miao, Alain Loiseau, Lin Lin, Jing Wan, Wei Liang, Anindya Nath, Sagar Premnath Karalkar, Souvick Mitra, Xunyu Li, Mengfu Di
-
Publication number: 20250089378Abstract: An electrostatic discharge (ESD) protection circuit includes a silicon controlled rectifier. The silicon controlled rectifier includes a first well of a first conductivity type in a substrate, and a first doped region of a second conductivity type and a first tap region of the first conductivity type in the first well. The second conductivity type has an opposite polarity to the first conductivity type. The first doped region is coupled to a first pad. The first tap region is coupled to a second pad through a resistor external to the silicon controlled rectifier.Type: ApplicationFiled: September 7, 2023Publication date: March 13, 2025Inventors: ALAIN F. LOISEAU, ANINDYA NATH, MENG MIAO, WEI LIANG, SOUVICK MITRA, ROBERT JOHN GAUTHIER, JR.
-
Patent number: 12205943Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.Type: GrantFiled: August 18, 2022Date of Patent: January 21, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Anindya Nath, Alain F. Loiseau, Souvick Mitra, Rajendran Krishnasamy
-
Publication number: 20250015074Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.Type: ApplicationFiled: September 16, 2024Publication date: January 9, 2025Inventors: Anindya Nath, Souvick Mitra
-
Patent number: 12191300Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.Type: GrantFiled: May 11, 2022Date of Patent: January 7, 2025Assignee: GlobalFoundries U.S. Inc.Inventors: Robert J. Gauthier, Jr., Rajendran Krishnasamy, Anupam Dutta, Anindya Nath, Xiangxiang Lu, Satyasuresh Vvss Choppalli, Lin Lin
-
Patent number: 12125842Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.Type: GrantFiled: June 3, 2022Date of Patent: October 22, 2024Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Anindya Nath, Souvick Mitra
-
Publication number: 20240347528Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.Type: ApplicationFiled: April 13, 2023Publication date: October 17, 2024Inventors: Anindya NATH, Rajendran KRISHNASAMY, Souvick MITRA, Steven M. SHANK, Sagar P. KARALKAR
-
Publication number: 20240339527Abstract: The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.Type: ApplicationFiled: April 6, 2023Publication date: October 10, 2024Inventors: Judson R. HOLT, John J. PEKARIK, Anindya NATH, Souvick MITRA
-
Publication number: 20240304612Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and a deep trench isolation structure between the plurality of shallow trench isolation structures and extending into the semiconductor material deeper than the plurality of shallow trench isolation structures.Type: ApplicationFiled: March 7, 2023Publication date: September 12, 2024Inventors: Shesh Mani PANDEY, Sagar Premnath KARALKAR, Rajendran KRISHNASAMY, Anindya NATH
-
Publication number: 20240290776Abstract: Embodiments of the disclosure provide a structure including a semiconductor substrate. The semiconductor substrate includes a porous semiconductor region, the porous semiconductor region including a cavity. The cavity includes a semiconductor layer therein. The porous semiconductor further includes a device. The device includes a first well at least partially in the semiconductor layer and a second well at least partially in the semiconductor layer and positioned laterally immediately adjacent the first well. The device further includes a first doped region abutting the first well; and a second doped region abutting the second well, wherein the first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity.Type: ApplicationFiled: February 23, 2023Publication date: August 29, 2024Inventors: Anindya Nath, Rajendran Krishnasamy, Robert J. Gauthier, JR.
-
Publication number: 20240266422Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.Type: ApplicationFiled: February 8, 2023Publication date: August 8, 2024Inventors: Anupam Dutta, Satyasuresh Vvss Choppalli, Rajendran Krishnasamy, Robert J. Gauthier, JR., Anindya Nath
-
Patent number: 12057444Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.Type: GrantFiled: June 23, 2022Date of Patent: August 6, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Souvick Mitra, Alain F. Loiseau, Robert J. Gauthier, Jr., Meng Miao, Anindya Nath, Wei Liang
-
Publication number: 20240234305Abstract: A structure includes: an electrically programmable fuse (e-fuse) including an anode and a cathode; at least one transistor positioned adjacent the e-fuse; and an electrically conductive interconnect coupling the cathode of the e-fuse to the at least one transistor, wherein the at least one transistor includes at least one semiconductor fin extending perpendicularly to the e-fuse.Type: ApplicationFiled: January 6, 2023Publication date: July 11, 2024Inventors: Shesh M. Pandey, Anindya Nath, Alain F. Loiseau, Souvick Mitra, Chung F. Tan, Judson R. Holt
-
Patent number: 11955472Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P? closer to insulator layer).Type: GrantFiled: December 17, 2021Date of Patent: April 9, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Meng Miao, Alain Loiseau, Souvick Mitra, Wei Liang, Robert J. Gauthier, Jr., Anindya Nath
-
Publication number: 20240105683Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Vvss Satyasuresh Choppalli, Anupam Dutta, Rajendran Krishnasamy, Robert Gauthier, JR., Xiang Xiang Lu, Anindya Nath
-
Publication number: 20240096874Abstract: The present disclosure relates to a structure including a trigger element within a semiconductor-on-insulator (SOI) substrate, and a silicon controlled rectifier (SCR) under a buried insulator layer of the SOI substrate. The trigger element is between an anode and a cathode of the SCR.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Inventors: Anindya NATH, Alain F. LOISEAU, Souvick MITRA