Patents by Inventor Anindya Poddar

Anindya Poddar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140653
    Abstract: An electronic device includes opposite first and second sides, opposite third and fourth sides spaced apart along a first direction, and opposite fifth and sixth sides spaced apart along a second direction orthogonal to the first direction, the first and second sides being spaced apart along a third direction orthogonal to the first and second directions. The electronic device includes a molded package, first leads exposed outside the molded package along the first side, and the first leads extending outward from the molded package along a respective one of the third and fourth sides, and second leads exposed outside the molded package along the first side, the second leads having a lateral side exposed outside the molded package along a respective one of the fifth and sixth sides, and the lateral side of the individual second leads being flush with a respective side of the molded package.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Inventors: Anindya Poddar, Ashok Prabhu, Hau Nguyen, Kurt Sincerbox, Makoto Shibuya
  • Patent number: 12272626
    Abstract: In some examples, a semiconductor package comprises a semiconductor die including a device side having a circuit; a mold compound covering the semiconductor die and the circuit; a first lead coupled to the circuit, the first lead having a gullwing shape and emerging from the mold compound in a first horizontal plane, the first lead having a distal end coincident with a second horizontal plane lower than a bottom surface of the mold compound; and a second lead coupled to the circuit, the second lead emerging from the mold compound in the first horizontal plane, the second lead having a distal end coincident with a third horizontal plane higher than a topmost surface of the mold compound, the distal end of the second lead vertically coincident with the mold compound.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 8, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Anindya Poddar
  • Publication number: 20250096768
    Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.
    Type: Application
    Filed: December 3, 2024
    Publication date: March 20, 2025
    Inventors: Anindya PODDAR, Hau NGUYEN, Masamitsu MATSUURA
  • Publication number: 20250087591
    Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
    Type: Application
    Filed: November 26, 2024
    Publication date: March 13, 2025
    Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
  • Publication number: 20250046684
    Abstract: A semiconductor package comprises an integrated circuit die covered by a mold compound to form a four-sided package with a top surface and a bottom surface. A first group of no-lead contacts are exposed on a first side and on the bottom surface of the package. A second group of no-lead contacts are exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side. A first external lead extends from a third side of the package. A second external lead extends from a fourth side of the package opposite the third side. The first and second external leads bent to extend above the top surface of the package. The first and second external leads have a gull-wing shape or a J-shape.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Makoto Shibuya, Yasmine Yan, Masamitsu Matsuura, Anindya Poddar
  • Publication number: 20240421120
    Abstract: A method includes forming a stress sensitive component on a first semiconductor die; forming a solder seal on the first semiconductor die, the solder seal extending from a first surface of the first semiconductor die, and surrounding the stress sensitive component, the solder seal having an interior surface that surrounds the stress sensitive component and having an exterior surface facing away from the stress sensitive component; flip chip mounting the first semiconductor die to a first surface of a second semiconductor die, the stress sensitive component facing the first surface of the second semiconductor die; and forming a solder joint between the solder seal and the first surface of the second semiconductor die.
    Type: Application
    Filed: August 27, 2024
    Publication date: December 19, 2024
    Inventors: Anindya Poddar, Mahmud Chowdhury, Hau Nguyen, Masamitsu Matsuura, Ting-Ta Yen
  • Patent number: 12160219
    Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: December 3, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Hau Nguyen, Masamitsu Matsuura
  • Publication number: 20240395731
    Abstract: An electronic device includes a leadframe having a die pad and leads. A die that includes an active layer is attached to the die pad. A reinforcement layer is disposed on the active layer and wire bonds are attached from the active layer of the die to the leads. A mold compound encapsulates the die, the reinforcement layer, and the wire bonds.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 28, 2024
    Inventors: Masamitsu Matsuura, Anindya Poddar, Daiki Komatsu, Hau Thanh Nguyen, Patrick Francis Thompson
  • Patent number: 12154861
    Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
  • Publication number: 20240363465
    Abstract: An electronic device includes a semiconductor die, a die attach pad, an adhesive, a conductive lead, and a package structure, where the semiconductor die has opposite first and second sides, a conductive terminal on the second side, and an electrical isolation coating layer that extends on the first side, the adhesive adheres the first side of the semiconductor die to the die attach pad, the conductive lead is electrically coupled to the conductive terminal of the semiconductor die, and the package structure encloses at least a portion of the semiconductor die.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Anindya Poddar, Daiki Komatsu, Hau Nguyen
  • Patent number: 12125799
    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 22, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
  • Publication number: 20240347441
    Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Anindya Poddar, Ashok Surendra Prabhu, Edgar Dorotyao Balidoy, Hau Nguyen, Makoto Yoshino, MING LI
  • Publication number: 20240332243
    Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Mahmud Halim CHOWDHURY, Amin SIJELMASSI, Murali KITTAPPA, Anindya PODDAR, Honglin GUO, Joe Adam GARCIA, John Paul TELLKAMP
  • Patent number: 12074134
    Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 27, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Mahmud Chowdhury, Hau Nguyen, Masamitsu Matsuura, Ting-Ta Yen
  • Patent number: 12057264
    Abstract: In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2nd layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 6, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Anindya Poddar
  • Patent number: 12021019
    Abstract: A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: June 25, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Ashok Surendra Prabhu, Edgar Dorotyao Balidoy, Hau Nguyen, Makoto Yoshino, Ming Li
  • Patent number: 12009336
    Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: June 11, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mahmud Halim Chowdhury, Amin Sijelmassi, Murali Kittappa, Anindya Poddar, Honglin Guo, Joe Adam Garcia, John Paul Tellkamp
  • Patent number: 11955456
    Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Ashok Surendra Prabhu, Hau Nguyen, Kurt Edward Sincerbox, Makoto Shibuya
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11923281
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Woochan Kim, Vivek Kishorechand Arora