Patents by Inventor Anirban Bandyopadhyay

Anirban Bandyopadhyay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200160174
    Abstract: Big data, which is too massive to analyze instantly, could cause various problems, including threats to the security by terrorism and intellectual crimes hiding behind its huge volume and complexity. Using topological information as key unit to encode information, every single piece of information is converted into a topology or geometric shape and encoded in a clock without requiring software programming by a human. Each of the converted piece of information itself indicates an event, a decision, etc. that has its own significance/meaning. Geometric shapes integrate within their single decision time and again to find the intricate pattern of any event, including the above-mentioned threats.
    Type: Application
    Filed: August 2, 2018
    Publication date: May 21, 2020
    Inventors: Anirban BANDYOPADHYAY, Subrata GHOSH, Daisuke FUJITA
  • Publication number: 20200160147
    Abstract: Artificial intelligence research is failing to produce true intelligence in spite of enormous resources. The reason is that programming is unavoidable for data processing and so there is no way to replace an user. In addition, because of data deluge problem, it is impossible to analyze all data as conventional information. Hardware inspired by prime metric is provided, where a metric of artificial intelligence is built in which unknown random events are linked as a changing geometric shape. All information is converted such that layered geometric shapes clocking in a pattern or event becomes unit of information, not insignificant bits. All complex events are considered as a single point to go ahead on building higher level geometric shapes as part of a time crystal following prime metric.
    Type: Application
    Filed: August 2, 2018
    Publication date: May 21, 2020
    Inventors: Anirban BANDYOPADHYAY, Subrata GHOSH, Daisuke FUJITA
  • Patent number: 9019685
    Abstract: A spiral capacitor-inductor device in which an array of unit capacitors 101 is arranged in a loop along the length is provided as the fourth circuit element. An input signal is applied to one end of the array of the unit capacitors, an output signal is taken out from the other end, an electric charge stored in each unit capacitor increases or decreases in accordance with increase or decrease in the bias applied to the device, the increase or decrease in the electric charge causes the current of the loop to increase or decrease, and, as a result, the magnetic flux 103 generated in the device varies. Accordingly, the fourth circuit element is provided that follows after an inductor, a capacitor, and a resistor is provided in which the electric charge stored determines the magnitude of its magnetic flux.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: April 28, 2015
    Assignee: National Institute for Materials Science
    Inventors: Satyajit Sahu, Anirban Bandyopadhyay, Daisuke Fujita
  • Publication number: 20130106538
    Abstract: A spiral capacitor-inductor device in which an array of unit capacitors 101 is arranged in a loop along the length is provided as the fourth circuit element. An input signal is applied to one end of the array of the unit capacitors, an output signal is taken out from the other end, an electric charge stored in each unit capacitor increases or decreases in accordance with increase or decrease in the bias applied to the device, the increase or decrease in the electric charge causes the current of the loop to increase or decrease, and, as a result, the magnetic flux 103 generated in the device varies. Accordingly, the fourth circuit element is provided that follows after an inductor, a capacitor, and a resistor is provided in which the electric charge stored determines the magnitude of its magnetic flux.
    Type: Application
    Filed: April 14, 2011
    Publication date: May 2, 2013
    Inventors: Satyajit Sahu, Anirban Bandyopadhyay, Daisuke Fujita
  • Publication number: 20060029325
    Abstract: A thermo-optic device may be formed with trenches that undercut the substrate beneath the thermo-optic device. Through the removal of the underlying substrate, the heat dissipation of the thermo-optic device may be reduced. This may reduce the thermal budget of the device, reducing the power requirements for operating the device in some embodiments.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 9, 2006
    Inventors: Behzad Fardi, Farshid Adibi, Chaoyang Li, Anirban Bandyopadhyay, Mahesh Junnarkab
  • Patent number: 6983086
    Abstract: A thermo-optic device may be formed with trenches that undercut the substrate beneath the thermo-optic device. Through the removal of the underlying substrate, the heat dissipation of the thermo-optic device may be reduced. This may reduce the thermal budget of the device, reducing the power requirements for operating the device in some embodiments.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: January 3, 2006
    Assignee: Intel Corporation
    Inventors: Behzad Fardi, Farshid Adibi, Chaoyang Li, Anirban Bandyopadhyay, Mahesh Junnarkar
  • Patent number: 6950581
    Abstract: Optical coupler apparatus having reduced geometry sensitivity includes spaced apart first and second main waveguides having a coupling section. In one embodiment, first and second side waveguide sections are arranged in the coupling section adjacent outer sides of the first and second main waveguides to allow evanescent coupling between the main waveguides and side waveguide sections. Methods of fabrication and operation are also described.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 27, 2005
    Assignee: Intel Corporation
    Inventor: Anirban Bandyopadhyay
  • Patent number: 6898347
    Abstract: An optical network may include a detector for detecting the power of each of a plurality of channels of a wavelength division multiplexed optical signal in one embodiment of the present invention. Each channel may be conveyed to an interface underneath a detector by way of a core formed in the substrate. The interface may include a trench with one side surface angled to form a reflector to reflect light upwardly to be detected by the detector. The trench may be filled with a convex microlens.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 24, 2005
    Assignee: Intel Corporation
    Inventors: Mahesh R. Junnarkar, Anirban Bandyopadhyay
  • Publication number: 20050063631
    Abstract: A temperature gradient may be provided across an array of waveguides in an arrayed waveguide grating. As a result, temperature tuning may be provided to adjust the characteristics of the arrayed waveguide grating. For example, the array of waveguides positioned on one side of a planar light wave circuit may be heated by a similarly configured array of heaters on the opposite side of the circuit. In some cases the number of heaters may be less than the number of arrayed waveguides. Also, each of the heaters in one embodiment may be selectively actuatable.
    Type: Application
    Filed: September 24, 2003
    Publication date: March 24, 2005
    Inventors: Mahesh Junnarkar, Anirban Bandyopadhyay
  • Publication number: 20040258344
    Abstract: A thermo-optic device may be formed with trenches that undercut the substrate beneath the thermo-optic device. Through the removal of the underlying substrate, the heat dissipation of the thermo-optic device may be reduced. This may reduce the thermal budget of the device, reducing the power requirements for operating the device in some embodiments.
    Type: Application
    Filed: June 19, 2003
    Publication date: December 23, 2004
    Inventors: Behzad Fardi, Farshid Adibi, Chaoyang Li, Anirban Bandyopadhyay, Mahesh Junnarkar
  • Publication number: 20040240783
    Abstract: An optical network may include a detector for detecting the power of each of a plurality of channels of a wavelength division multiplexed optical signal in one embodiment of the present invention. Each channel may be conveyed to an interface underneath a detector by way of a core formed in the substrate. The interface may include a trench with one side surface angled to form a reflector to reflect light upwardly to be detected by the detector. The trench may be filled with a convex microlens.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: Mahesh R. Junnarkar, Anirban Bandyopadhyay
  • Publication number: 20040240770
    Abstract: A planar light wave circuit may include a directional coupler with two waveguides come close to one another in a so-called gap region. Polarization dependent coupling may be reduced by forming trenches on either side of the gap region to reduce birefringence.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Inventors: Mahesh R. Junnarkar, Anirban Bandyopadhyay
  • Publication number: 20040013357
    Abstract: Optical coupler apparatus having reduced geometry sensitivity includes spaced apart first and second main waveguides having a coupling section. In one embodiment, first and second side waveguide sections are arranged in the coupling section adjacent outer sides of the first and second main waveguides to allow evanescent coupling between the main waveguides and side waveguide sections. Methods of fabrication and operation are also described.
    Type: Application
    Filed: July 22, 2002
    Publication date: January 22, 2004
    Applicant: Intel Corporation
    Inventor: Anirban Bandyopadhyay